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standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 604 .415.6000 pm6344 equad quadruple e1 framer issue 5: june 1998
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer i contents 1 features ...................................................................................................................... ..1 2 applications .................................................................................................................4 3 references ..................................................................................................................5 4 application examples ...............................................................................................7 5 block diagram .............................................................................................................8 6 pin diagram .................................................................................................................11 7 pin description .........................................................................................................12 8 functional description ........................................................................................29 8.1 digital receive interface (drif) .............................................................29 8.2 clock and data recovery (cdrc) ...........................................................29 8.3 framer (frmr) ...............................................................................................31 8.4 performance monitor counters (pmon)...........................................38 8.5 hdlc receiver (rfdl) ..................................................................................38 8.6 elastic store (elst) ...................................................................................39 8.7 signaling extractor (sigx) .....................................................................39 8.8 backplane receive interface (brif) .....................................................40 8.9 transmitter (tran) .....................................................................................40 8.10 transmit per-channel serial controller (pcsc) ..........................41 8.11 hdlc transmitter (xfdl) ...........................................................................41 8.12 digital jitter attenuator (djat) .............................................................42 8.13 timing options (tops) .................................................................................46 8.14 digital e1 transmit interface (dtif) .....................................................46 8.15 backplane transmit interface (btif) ...................................................47
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer ii 8.16 microprocessor interface (mpif) ........................................................47 9 register description .............................................................................................48 10 normal mode register description.................................................................52 10.1 sigx indirect registers 96 (60h) - 127 (7fh) - segment 4: typical per-timeslot configuration and signaling trunk ......................156 10.2 registers 049-04fh, 0c9h-0cfh, 149h-14fh, 1c9h-1cfh: latching performance data.....................................................................................168 11 test features description ................................................................................176 11.1 test mode 0 ..................................................................................................176 12 functional timing...................................................................................................180 12.1 receive backplane interface...............................................................182 13 operation ..................................................................................................................19 1 13.1 using the internal fdl transmitter .................................................192 13.2 using the internal fdl receiver.........................................................194 13.3 using the loopback modes....................................................................201 13.3.1 payload loopback ........................................................................202 13.3.2 line loopback ................................................................................203 13.3.3 diagnostic digital loopback ...................................................203 13.4 using the per-channel serial controllers ..................................204 13.4.1 initialization ...................................................................................204 13.4.2 direct access mode ....................................................................205 13.4.3 indirect access mode ................................................................205 13.5 using the digital jitter attenuator ..................................................206 13.5.1 default application .....................................................................206 13.5.2 data burst application ...............................................................206
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer iii 13.5.3 elastic store application ........................................................207 13.5.4 alternate tclko reference application.............................207 13.5.5 changing the jitter transfer function ............................208 13.5.6 receiver jitter attenuation ....................................................208 13.6 using the performance monitor counter values ......................210 13.7 reset procedure ......................................................................................212 14 absolute maximum ratings .................................................................................216 15 capacitance...............................................................................................................217 16 d.c. characteristics.............................................................................................218 17 microprocessor interface timing characteristics...............................220 18 equad i/o timing characteristics ....................................................................225 19 ordering and thermal information ...............................................................239 20 mechanical information......................................................................................240
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer iv list of registers register 000h, 080h, 100h, 180h: receive options .......................................................53 register 001h, 081h, 101h, 181h: receive backplane options .................................56 register 002h, 082h, 102h, 182h: datalink options.......................................................60 register 003h, 083h, 103h, 183h: receive interface configuration .....................63 register 004h, 084h, 104h, 184h: transmit interface configuration ..................65 register 005h, 085h, 105h, 185h: transmit backplane options...............................68 register 006h, 086h, 106h, 186h: transmit framing options ...................................70 register 007h, 087h, 107h, 187h: transmit timing options........................................72 register 008h, 088h, 108h, 188h: interrupt source....................................................77 register 009h, 089h, 109h, 189h: receive ts0 data link enables .............................78 register 00ah, 08ah, 10ah, 18ah: master diagnostics ..............................................80 register 00bh, 20bh: equad master test ......................................................................82 register 00ch: equad revision/chip id/global pmon update ................................84 register 00dh, 08dh, 10dh, 18dh: framer reset..........................................................85 register 00eh, 08eh, 10eh, 18eh: phase status word (lsb) ......................................86 register 00fh, 08fh, 10fh, 18fh: phase status word (msb)......................................88 register 010h, 090h, 110h, 190h: cdrc configuration ...............................................89 register 011h, 091h, 111h, 191h: cdrc interrupt enable .........................................91 register 012h, 092h, 112h, 192h: cdrc interrupt status ..........................................92 register 013h, 093h, 113h, 193h: cdrc alternate loss of signal status............94 registers 014h, 094h, 114h and 194h: channel select (0 to 7) ................................95 registers 015h, 095h, 115h and 195h: channel select (8 to 15) ..............................96 registers 016h, 096h, 116h and 196h: channel select (16 to 23) ............................97
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer v registers 017h, 097h, 117h and 197h: channel select (24 to 31) ............................98 register 018h, 098h, 118h, 198h: djat interrupt status ............................................99 register 019h, 099h, 119h, 199h: djat reference clock divisor (n1) control100 register 01ah, 09ah, 11ah, 19ah: djat output clock divisor (n2) control.....101 register 01bh, 09bh, 11bh, 19bh: djat configuration..............................................102 register 01ch, 09ch, 11ch, 19ch: elst configuration ............................................104 register 01dh, 09dh, 11dh, 19dh: elst interrupt status .......................................105 register 01eh, 09eh, 11eh, 19eh: elst idle code .......................................................106 register 020h, 0a0h, 120h, 1a0h: frmr frame alignment options ......................107 register 021h, 0a1h, 121h, 1a1h: frmr maintenance mode options ...................109 register 022h, 0a2h, 122h, 1a2h: frmr framing status interrupt enable.......111 register 023h, 0a3h, 123h, 1a3h: frmr maintenance/alarm status interrupt enable......................................................................................................................... 112 register 024h, 0a4h, 124h, 1a4h: frmr framing status interrupt indication.113 register 025h, 0a5h, 125h, 1a5h: frmr maintenance/alarm status interrupt indication...................................................................................................................11 4 register 026h, 0a6h, 126h, 1a6h: frmr framing status ...........................................115 register 027h, 0a7h, 127h, 1a7h: frmr maintenance/alarm status ....................117 register 028h, 0a8h, 128h, 1a8h: frmr international/national bits ..................119 register 029h, 0a9h, 129h, 1a9h: frmr extra bits .....................................................120 register 02ah, 0aah, 12ah, 1aah: frmr crc error counter - lsb ......................121 register 02bh, 0abh, 12bh, 1abh: frmr crc error counter - msb .....................122 register 02ch, 0ach, 12ch, 1ach: ts16 ais alarm status.........................................123 register 030h, 0b0h, 130h, 1b0h: tpsc block configuration ................................124 register 031h, 0b1h, 131h, 1b1h: tpsc block p access status............................125
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer vi register 032h, 0b2h, 132h, 1b2h: tpsc block timeslot indirect address/control ...................................................................................................126 register 033h, 0b3h, 133h, 1b3h: tpsc block timeslot indirect data buffer..127 tpsc internal registers 20-3fh: data control byte..............................................129 tpsc internal registers 40-5fh: idle code byte .....................................................131 register 034h, 0b4h, 134h, 1b4h: xfdl block configuration ................................132 register 035h, 0b5h, 135h, 1b5h: xfdl interrupt status.........................................134 register 036h, 0b6h, 136h, 1b6h: xfdl transmit data................................................135 register 038h, 0b8h, 138h, 1b8h: rfdl configuration .............................................136 register 039h, 0b9h, 139h, 1b9h: rfdl interrupt control/status ......................137 register 03ah, 0bah, 13ah, 1bah: rfdl status ............................................................139 register 03bh, 0bbh, 13bh, 1bbh: rfdl receive data ................................................142 registers 03ch, 0bch, 13ch and 1bch: interrupt id/clock monitor.................143 registers 03dh, 0bdh, 13dh and 1bdh: backplane parity configuration and status......................................................................................................................... .145 register 040h, 0c0h, 140h, 1c0h: sigx block configuration.................................147 register 041h, 0c1h, 141h, 1c1h: sigx block p access status ............................149 register 042h, 0c2h, 142h, 1c2h: sigx block time slot indirect address/control ...................................................................................................150 register 043h, 0c3h, 143h, 1c3h: sigx block time slot indirect data buffer .151 sigx indirect registers 33 (21h)- 47 (2fh) - segment 2: typical timeslot signaling data register (tss 1-15) ....................................................................153 sigx indirect registers 49 (31h)- 63 (3fh) - segment 2: typical timeslot signaling data register (tss 17-31) ..................................................................154 sigx indirect registers 64 (40h) - 95 (5fh) - segment 3: typical per-timeslot pcm trunk conditioning data register .........................................................155 conditioning data register.............................................................................................156
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer vii register 044h, 0c4h, 144h, 1c4h: tran configuration.............................................158 register 045h, 0c5h, 145h, 1c5h: tran transmit alarm/diagnostic control .162 register 046h, 0c6h, 146h, 1c6h: tran international/national control .........164 register 047h, 0c7h, 147h, 1c7h: tran extra bits control ...................................166 register 048h, 0c8h, 148h, 1c8h: pmon control/status..........................................167 register 049h, 0c9h, 149h, 1c9h: framing bit error count ..................................169 register 04ah, 0cah, 14ah, 1cah: far end block error count lsb ...................170 register 04bh, 0cbh, 14bh, 1cbh: far end block error count msb ..................171 register 04ch, 0cch, 14ch, 1cch: crc error count lsb .......................................172 register 04dh, 0cdh, 14dh, 1cdh: crc error count msb ......................................173 register 04eh, 0ceh, 14eh, 1ceh: line code violation count lsb .......................174 register 04fh, 0cfh, 14fh, 1cfh: line code violation count msb.......................175
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer viii list of figures figure 1 - example 1. ds-3 terminal multiplexer/channel bank........................7 figure 2 - cdrc jitter tolerance with algsel = 1................................................30 figure 3 - cdrc jitter tolerance with algsel = 0................................................31 figure 4 - basic framing algorithm flowchart...................................................34 figure 5 - djat jitter tolerance.................................................................................44 figure 6 - djat minimum jitter tolerance vs. xclk accuracy ..........................45 figure 7 - djat jitter transfer ...................................................................................46 figure 8 - transmit timing options ............................................................................76 figure 9 - ts16 receive datalink interface............................................................180 figure 10 - ts0 receive datalink interface..............................................................180 figure 11 - ts16 transmit datalink interface .........................................................181 figure 12 - ts0 transmit datalink interface ...........................................................181 figure 13 - rohm=0, brx2rail=0, brxsmfp=0 and brxcmfp=0..............................182 figure 14 - receive composite multiframe output (brxsmfp=1 and brxcmfp=1) ......................................................................................................183 figure 15 - receive overhead output (rohm=1) ....................................................183 figure 16 - elstbyp=1, srsmfp=1, srcmfp=1, brxsmfp=1, brxcmfp=0 .............184 figure 17 - receive channel interface ....................................................................184 figure 18 - transmit backplane interface .............................................................185 figure 19 - transmit channel interface..................................................................185 figure 20 - multiplexed receive backplane interface ......................................186 figure 21 - multiplexed transmit backplane interface ....................................188 figure 22 - multiplexed transmit backplane interface with btxmfp=1 ......190
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer ix figure 23 - typical data frame .....................................................................................197 figure 24 - rfdl normal data and abort sequence.............................................198 figure 25 - rfdl fifo overrun......................................................................................199 figure 26 - xfdl normal data sequence...................................................................200 figure 27 - xfdl underrun sequence .......................................................................201 figure 28 - payload loopback ......................................................................................202 figure 29 - line loopback ..............................................................................................203 figure 30 - diagnostic digital loopback .................................................................204 figure 31 - receive backplane interface with rclkosel = 1............................209 figure 32 - lcv count vs. ber........................................................................................211 figure 33 - fer count vs. ber .......................................................................................211 figure 34 - crce count vs. ber ....................................................................................212 figure 35 - microprocessor read access timing ................................................221 figure 36 - microprocessor write access timing...............................................223 figure 37 - backplane transmit input timing diagram .......................................225 figure 38 - backplane transmit input timing diagram .......................................226 figure 39 - xclk=37.056 mhz input timing ..................................................................227 figure 40 - tclki input timing........................................................................................228 figure 41 - digital receive interface input timing diagram.............................229 figure 42 - transmit data link input timing diagram ...........................................230 figure 43 - backplane receive timing diagram......................................................231 figure 44 - backplane receive timing (rclkosel = 1) diagram .........................232 figure 45 - multiplexed backplane receive timing diagram ............................233 figure 46 - receive data link output timing diagram..........................................234
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer x figure 47 - recovered frame output timing diagram........................................234 figure 48 - transmit interface output timing diagram.....................................235 figure 49 - transmit data link dma interface output timing diagram .........236 figure 50 - receive data link dma interface output timing diagram ............237 figure 51 - 128 pin copper leadframe plastic quad flat pack (r suffix) ....240
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer xi list of tables table 1 - normal mode register memory map.....................................................48 table 2 - ....................................................................................................................... .......74 table 3 - ....................................................................................................................... .......87 table 4 - ....................................................................................................................... .....177 table 5 - ....................................................................................................................... .....177 table 6 - configuring the equad from reset ...................................................191 table 7 - ....................................................................................................................... .....210 table 8 - equad capacitance.....................................................................................217 table 9 - equad d.c. characteristics....................................................................218 table 10 - microprocessor read access (figure 35) .......................................220 table 11 - microprocessor write access (figure 36) ......................................222 table 12 - backplane transmit input timing, menb input high (figure 37).225 table 13 - backplane transmit input timing, menb input low (figure 37)..226 table 14 - xclk=49.152 mhz input (figure 39)..........................................................227 table 15 - tclki input (figure 40 ................................................................................227 table 16 - digital receive interface input timing (figure 41) ........................228 table 17 - transmit data link input timing (figure 42) .......................................230 table 18 - backplane receive timing, menb input high (figure 43) ...............231 table 19 - backplane receive timing, menb input high, rclkosel = 1 (figure 44) ........................................................................................................................232 table 20 - multiplexed backplane receive timing, menb input low (figure 45) ........................................................................................................................233 table 21 - receive data link output timing (figure 46) .....................................234 table 22 - recovered frame pulse output timing (figure 47).......................234
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer xii table 23 - transmit interface output timing (figure 48) ................................235 table 24 - transmit data link dma interface output timing (figure 49) .....236 table 25 - receive data link dma interface output timing (figure 50) .......237 table 26 - equad ordering information ................................................................239 table 27 - equad thermal information...................................................................239
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 1 1 features integrates four full-featured e1 framers and transmitters in a single device for terminating duplex e1 signals. software and functionally compatible with the pm6341 e1xc single e1 transceiver. pin compatible with the pm4344 quad t1 framer device. provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring. low power cmos technology available in a 128 pin pqfp package. each one of four receiver sections: recovers clock and data using a digital phase locked loop for high jitter tolerance. a direct clock input is provided to allow clock recovery to be by- passed. accepts dual rail or single rail digital pcm inputs. supports hdb3 or ami line code. accepts gapped data streams to support higher rate demultiplexing. frames to a g.704 2048 kbit/s signal within 1 ms. frames to the signaling multiframe alignment when enabled. frames to the crc multiframe alignment when enabled. provides loss of signal detection, and indicates loss of frame alignment (oof), loss of signaling multiframe alignment and loss of crc multiframe alignment. supports line and path performance monitoring according to itu-t recommendations. accumulators are provided for counting: crc-4 errors to 1000 per second;
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 2 far end block errors to 1000 per second; frame sync errors to 127 per second; and line code violations to 8191 per second. indicates the reception of remote alarm and remote multiframe alarm. indicates the reception of alarm indication signal (ais) and time slot 16 ais. declares red and ais alarms using q.516 recommended integration periods. provides an hdlc/lapd interface for terminating a data link. supports polled, interrupt-driven, or dma servicing of the hdlc interface. optionally extracts the data link from timeslot 16 (64 kbit/s), which may be used to receive common channel signaling, or from any combination of the national bits in timeslot 0 of non-frame alignment signal frames (4 kbit/s - 20 kbit/s). supports fractional e1 channel extraction. provides a two-frame elastic store buffer for jitter and wander attenuation that performs controlled slips and indicates slip occurrence and direction. provides channel associated signaling extraction, with optional data inversion, programmable idle code substitution, and up to 3 multiframes of signaling debounce on a per-timeslot basis. provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all timeslots or on selected timeslots. optionally provides dual rail digital pcm output signals to allow bpv transparency. also supports unframed mode. supports transfer of pcm and signaling data to 2.048 mbit/s or 16.384mbit/s backplane buses. can be configured to attenuate jitter on the receive side by placing the digital jitter attenuator in the receive path.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 3 each one of four transmitter sections: formats data to create a g.704 2048 kbit/s signal. optionally inserts signaling multiframe alignment signal. optionally inserts crc multiframe structure including optional transmission of far end block errors. optionally accepts dual rail digital pcm inputs to allow bpv transparency. also supports unframed mode and framing bit, crc, or data link by-pass. supports transfer of pcm and signaling data from 2.048 mbit/s or 16.384mbit/s backplane buses. provides channel associated signaling insertion, programmable idle code substitution, digital milliwatt code substitution, and data inversion on a per timeslot basis. provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all timeslots or on selected timeslots. supports transmission of the alarm indication signal (ais), timeslot 16 ais, remote alarm signal or remote multiframe alarm signal. provides an hdlc/lapd interface for generating a data link. supports polled, interrupt-driven, or dma servicing of the hdlc interface. optionally inserts the data link into timeslot 16 (64 kbit/s), which may be used to transmit common channel signaling, or into any combination of the national bits in timeslot 0 of non-frame alignment signal frames (4 kbit/s - 20 kbit/s). supports fractional e1 channel insertion. provides a digital phase locked loop for generation of a low jitter transmit clock. provides a fifo buffer for jitter attenuation and rate conversion in the transmitter. fifo full or empty indication allows for bit-stuffing in higher rate multiplexing applications. supports hdb3 or ami line code. provides dual rail or single rail digital pcm output signals.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 4 2 applications e1 channel service units (csu) and data service units (dsu) e1 channel banks and multiplexers digital private branch exchanges (pbx) digital access and cross-connect systems (dacs) and electronic dsx cross-connect systems (edsx) e1 frame relay interfaces e1 atm interfaces isdn primary rate interfaces (pri) sdh byte synchronous tu12 mappers test equipment
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 5 3 references 1. itu-t recommendation g.704, - "synchronous frame structures used at primary and secondary hierarchical levels", vol. iii, fascicle iii.4, 1988. 2. itu-t recommendation g.706, - "frame alignment and cyclic redundancy check (crc) procedures relating to basic frame structures defined in recommendation g.704", vol. iii, fascicle iii.4 , 1988. 3. itu-t recommendation g.706, - "frame alignment and cyclic redundancy check (crc) procedures relating to basic frame structures defined in recommendation g.704", 1991 4. itu-t recommendation g.711, - "pulse code modulation (pcm) of voice frequencies", volume iii, fascicle iii.3, 1988. 5. itu-t recommendation g.732, - "characteristics of primary pcm multiplex equipment operating at 2048 kbit/s", vol. iii, fascicle iii.4, 1988. 6. itu-t recommendation g.735, - "characteristics of primary pcm multiplex equipment operating at 2048 kbit/s and offering synchronous digital access at 384 kbit/s and/or 64 kbit/s", vol. iii, fascicle iii.4, 1988. 7. itu-t recommendation g.821, - "error performance of an international digital connection forming part of an integrated services digital network", vol. iii, fascicle iii.5, 1988. 8. itu-t recommendation g.823, - "the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy", vol. iii, fascicle iii.5, 1988. 9. itu-t recommendation o.151, - "error performance measuring equipment for digital systems at the primary bit rate and above", vol. iv, fascicle iv.4, 1988. 10. itu-t blue book, recommendation o.162, - "equipment to perform in service monitoring on 2048 kbit/s signals", vol. iv, fascicle iv.4, 1988. 11. itu-t recommendation q.506, - "operations and maintenance functions", vol. vi, fascicle vi.5, 1984. 12. itu-t recommendation q.516, - "operations and maintenance functions", vol. vi, fascicle vi.5, 1984.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 6 13. transmission and multiplexing (tm); generic functional requirements for sdh transmission equipment, part 1: generic processes and performance", etsi de/tm-1015, november, 1993, version 1.0.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 7 4 application examples figure 1 - example 1. ds-3 terminal multiplexer/channel bank pm6344 equad pm6344 equad synchronous ds0 backplane pm8313 d3mx ds3 liu dsx-3 4 e1s services 4 e1s pm6344 equad pm6344 equad 4 e1s 4 e1s pm6341 e1xc 1 e1 pm6344 equad 4 e1s example 1 shows a ds-3 terminal multiplexer/channel bank using 5 equad devices, pmc-sierra's pm8313 d3mx m13 multiplexer, the pm6341 e1xc e1 transceiver, and silicon system's ssi 78p236 ds-3 line interface unit. 21 e1 signals can be multiplexed into a dsx-3 formatted signal. five equad devices and a single e1xc device are used to terminate these 21 signals. the ds-0 backplane data is transmitted and received using a 2.048 mhz system clock.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 8 5 block diagram rfdl hdlc receiver pmon performance monitor counters brif backplane receive interface elst elastic store sigx signalling extractor, trunk condition xfdl hdlc transmitter tran basictransmitter: frame generation, alarm insertion, trunk conditioning line coding pcsc per-channel controller: signalling, idle insert dtif digital transmit interface btif backplane transmit interface tops timing options receiver transmitter internal bus mpif micro- processor interface brpcm/brdp[1:4] brsig/brdn[1:4] brfpo[1:4] rclko[1:4] rfp[1:4] rdlclk/ rdleom[1:4] rdlsig/ rdlint[1:4] tdp/tdd[1:4] tclko[1:4] tdn/tflg[1:4] tdlsig/ tdlint[1:4] tdlclk/ tdludr[1:4] mrd* * these signals are shared between all four framers. xclk/vclk* rdn/rlcv[1:4] btpcm/btdp[1:4]/ mtd* btsig/btdn[1:4] brfpi*/mrfpi* brclk*/mrclk* rclki[1:4] rdp/rdd[1:4] tclki[1:4] btclk[1:4]/ mtclk* btfp[1:4]/mtfp* intb* d[7:0]* a[9:0]* rdb* wrb* csb* ale* rstb* menb* cdrc clock and data recovery djat digital jitter attenuator djat digital jitter attenuator optional connections are shown with dashed lines. frmr framer: frame alignment, alarm detection drif ds-1 receive interface optional placement
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 9 description the pm6344 quadruple e1 framer (equad) is a feature-rich device suitable for use in many e1 systems with a minimum of external circuitry. each of the framers and transmitters is independently software configurable, allowing feature selection without changes to external wiring. on the receive side, the equad recovers clock and data and can be configured to frame to a basic g.704 2048 kbit/s signal or also frame to the signaling multiframe alignment signal and the crc multiframe alignment signal. the equad also supports detection of various alarm conditions such as loss of signal, loss of frame, loss of signaling multiframe, loss of crc multiframe, and reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and timeslot 16 alarm indication signal. the equad detects and indicates the presence of remote alarm and ais patterns and also integrates red and ais alarms as per industry specifications. performance monitoring with accumulation of crc-4 errors, far end block errors, framing bit errors, and line code violation is provided. the equad also detects and terminates hdlc messages on a data link. the data link may be extracted from timeslot 16 and used for common channel signaling or may be extracted from the national bits. an elastic store for slip buffering and adaptation to backplane timing is provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a per-channel basis. receive side data and signaling trunk conditioning is also provided. on the transmit side, the equad generates framing for a basic g.704 2048 kbit/s signal, or framing can be optionally disabled. the signaling multiframe alignment structure may be optionally inserted and the crc multiframe structure may be optionally inserted. channel associated signaling insertion, idle code substitution, digital milliwatt tone substitution, and data inversion on a per-timeslot basis is also supported. transmit side data and signaling trunk conditioning is provided. hdlc messages on a data link can be transmitted. the data link may be inserted into timeslot 16 and used for common channel signaling or may be inserted into the national bits. the equad can generate a low jitter transmit clock and provides a fifo for transmit jitter attenuation. when not used for jitter
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 10 attenuation, the full or empty status of this fifo is made available to facilitate higher order multiplexing applications by controlling bit-stuffing logic. the equad provides a parallel microprocessor interface for controlling the operation of the equad device. serial pcm interfaces allow 2.048 mbit/s backplanes to be directly supported. tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. optional bit interleaved multiplexing of the individual serial streams supports 16.384 mbit/s backplanes.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 11 6 pin diagram the equad is packaged in a 128-pin plastic qfp package having a body size of 14 mm by 20 mm and a pin pitch of 0.5 mm. pin 1 pin 128 pm6344 equad top view pin 38 pin 39 pin 64 pin 65 pin 102 pin 103 index pin pha[3] pla[3] phd[2] pld[2] pha[4] pla[4] phd[3] pld[3] pha[2] pla[2] rclko[4] rclko[3] rclko[2] rclko[1] rfp[4] rfp[3] rfp[2] rfp[1] tclki[4] tclki[3] tclki[2] tclki[1] btclk[4] btclk[3] btclk[2] btclk[1]/mtclk brsig[4]/brdn[4] brsig[3]/brdn[3] brsig[2]/brdn[2] brsig[1]/brdn[1] brfpo[4] brfpo[3] brfpo[2] brfpo[1] btfp[4] btfp[3] btfp[2] btfp[1]/mtfp btsig[4]/btdn[4] btsig[3]/btdn[3] btsig[2]/btdn[2] btsig[1]/btdn[1] brpcm[1]/brdp[1] brpcm[2]/brdp[2] brpcm[3]/brdp[3] brpcm[4]/brdp[4] brfpi/mrfpi brclk/mrclk tdlclk[1]/tdludr[1] tdlclk[2]/tdludr[2] tdlclk[3]/tdludr[3] tdlclk[4]/tdludr[4] tdlsig[1]/tdlint[1] tdlsig[2]tdlint[2] tdlsig[3]/tdlint[3] tdlsig[4]/tdlint[4] rdlclk[1]/rdleom[1] rdlclk[2]/rdleom[2] rdlclk[3]/rdleom[3] rdlclk[4]/rdleom[4] rdlsig[1]/rdlint[1] rdlsig[2]/rdlint[2] rdlsig[3]/rdlint[3] rdlsig[4]/rdlint[4] d[2] d[1] d[0] menb csb rdb wrb ale rstb a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] tclko[4] tclko[3] tclko[1] tdp[1]/tdd[1] tdn[1]/tflg[1] tclko[2] rclki[3] rclki[4] rdn[2]/rlcv[2] rclki[2] rdp[1]/rdd[1] rdn[1]/rlcv[1] rclki[1] rdp[2]/rdd[2] btpcm[4]/btdp[4] btpcm[3]/btdp[3] btpcm[2]/btdp[2] btpcm[1]/btdp[1]/mtd xclk/vclk mrd intb d[7] d[6] d[5] d[4] d[3] pld[1] phd[1] pla[1] pha[1] pla[5] pha[0] pla[0] phd[0] pld[0] rdn[3]/rlcv[3] rdp[3]/rdd[3] rdn[4]/rlcv[4] rdp[4]/rdd[4] tdp[2]/tdd[2] tdn[2]/tflg[2] tdp[3]/tdd[3] tdn[3]/tflg[3] tdp[4]/tdd[4] tdn[4]/tflg[4]
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 12 7 pin description pin name type pin no. function menb input 45 multiplex enable (menb). when this input is asserted low, the four sets of pcm and signaling streams are combined into a single bit interleaved 16.384 mbit/s serial stream. in the transmit direction, all data is expected on mtd with alignment indicated by mtfp. mtd and mtfp are sampled on the rising edge of mtclk. in the receive direction, data is presented on mrd aligned with mrfpi. mrfpi is sampled on the rising edge of mrclk and mrd is updated on the falling edge of mrclk. when this input is deasserted high, each pcm and signaling stream has its own dedicated pin. menb has an integral pull-up. rdp[1] rdp[2] rdp[3] rdp[4] / input 2 5 8 11 receive positive line pulse (rdp[4:1]). these inputs are available when the equad is configured to receive dual-rail formatted data. the rdp[4:1] inputs may be enabled for either rz or nrz waveforms. when enabled for nrz, this input may be enabled to be sampled on the rising or falling edge of the corresponding rclki[4:1]. when enabled for rz, the clocks are recovered from the corresponding rdp[4:1] and rdn[4:1] inputs. rdd[1] rdd[2] rdd[3] rdd[4] receive digital e1 signal (rdd[4:1]). when the equad is configured to receive single-rail data, these inputs may be enabled to be sampled on the rising or falling edge of the corresponding rclki[4:1].
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 13 pin name type pin no. function rdn[1] rdn[2] rdn[3] rdn[4] / input 3 6 9 12 receive digital negative line pulse (rdn[4:1]). these inputs are available when the equad is configured to receive dual-rail formatted data. the rdn[4:1] inputs may be enabled for either rz or nrz waveforms. when enabled for nrz, these inputs may be enabled to be sampled on the rising or falling edge of the corresponding rclki[4:1]. when enabled for rz, the clocks are recovered from the corresponding rdp[4:1] and rdn[4:1] inputs. rlcv[1] rlcv[2] rlcv[3] rlcv[4] receive line code violation indication (rlcv[4:1]). when the equad is configured to receive single-rail data, this input may be enabled to be sampled on the rising or falling edge of the corresponding rclki[4:1]. rclki[1] rclki[2] rclki[3] rclki[4] input 4 7 10 13 receive line clock inputs (rclki[4:1]). each input is an externally recovered 2.048 mhz line clock that may be enabled to sample the rdp[x] and rdn[x] inputs on its rising or falling edge when the input format is enabled for dual-rail nrz; or to sample the rdd[x] and rlcv[x] inputs on its rising or falling edge when the input format is enabled for single-rail. rclko[1] rclko[2] rclko[3] rclko[4] output 87 88 91 92 recovered pcm clock output (rclko[4:1]). each output signal is the recovered 2.048 mhz clock, synchronized to the xclk signal. each rclko[x] signal is recovered from the rdp[x] and rdn[x] inputs (if the input format is dual-rail rz) or from the rclki[x] input (if the input format is nrz). when the elst is by-passed or the rclkosel register bit is set, brpcm[x] and brsig[x] are updated on the falling edge of the associated rclko[x]. as an option, the digital attenuator's smooth 2.048 mhz clock may be presented on rclko[x]. see the operations section for details on this application.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 14 pin name type pin no. function rfp[1] rfp[2] rfp[3] rfp[4] output 81 82 83 84 receive frame pulse (rfp[4:1]). the rfp[x] outputs are intended as a timing references. when the equad is configured for receive frame pulse output, rfp[x] pulses high for 1 rclko cycle during bit 1 of each 256-bit frame, indicating the frame alignment of the receive stream. when configured for receive signaling multiframe output, rfp[x] pulses high for 1 rclko[x] cycle during bit 1 of frame 1 of the 16 frame signaling multiframe, indicating the signaling multiframe alignment of the receive stream. (even when signaling multiframing is disabled, the rfp[x] output continues to indicate the position of bit 1 of every 16 th frame.) when configured for receive crc multiframe output, rfp[x] pulses high for 1 rclko[x] cycle during bit 1 of frame 1 of every 16 frame crc multiframe, indicating the crc multiframe alignment of the receive stream. (even when crc multiframing is disabled, the rfp[x] output continues to indicate the position of bit 1 of the fas frame every 16 th frame.) when configured for composite multiframe output, rfp[x] goes high on the falling rclko[x] edge marking the beginning of bit 1 of frame 1 of every 16 frame signaling multiframe, indicating the signaling multiframe alignment of the receive stream, and returns low on the falling rclko[x] edge marking the ending of bit 1 of frame 1 of every 16 frame crc multiframe, indicating the crc multiframe alignment of the receive stream. this mode allows both multiframe alignments to be decoded externally from the single rfp[x] signal. note that if the signaling and crc multiframe alignments are coincident, rfp[x] will pulse high for 1 rclko[x] cycle every 16 frames. each rfp[x] is updated on the falling edge of the associated rclko[x]. rfp[x] should not be used when register bit rclkosel is set to a logic 1.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 15 pin name type pin no. function rdlsig[1] rdlsig[2] rdlsig[3] rdlsig[4]/ output 125 126 127 128 receive data link signal (rdlsig[4:1]). the rdlsig[4:1] signals are available on these outputs when the associated internal hdlc receiver (rfdl) is disabled from use, or, optionally, when fractional e1 is extracted. rdlsig contains the data link stream extracted from the selected data link bits. the equad may be configured to utilize timeslot 16 as a data link or utilize any combination of the national bits as a data link. each rdlsig[x] is updated on the falling edge of the associated rdlclk[x]. rdlint[1] rdlint[2] rdlint[3] rdlint[4] receive data link interrupt (rdlint[4:1]). the rdlint[4:1] signals are available on these outputs when the associated rfdl is enabled. each rdlint[x] goes high when an event occurs which changes the status of the associated hdlc receiver. rdlclk[1] rdlclk[2] rdlclk[3] rdlclk[4]/ output 119 120 123 124 receive data link clock (rdlclk[4:1]). the rdlclk[4:1] signals are available on these outputs when the associated internal hdlc receiver (rfdl) is disabled from use, or, optionally, when fractional e1 is extracted. the rising edge of rdlclk[x] can be used to sample the data-link data or the fractional e1 data on the associated rdlsig[x] when the internal hdlc receiver is disabled or when fractional e1 is enabled respectively. rdleom[1] rdleom[2] rdleom[3] rdleom[4] receive data link end of message (rdleom[4:1]). the rdleom[4:1] signals are available on these outputs when the associated rfdl is enabled. each rdleom[x] goes high when the last byte of a received sequence is read from the associated rfdl fifo buffer, or when the fifo buffer is overrun.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 16 pin name type pin no. function brpcm[1] brpcm[2] brpcm[3] brpcm[4]/ output 103 104 107 108 backplane receive pcm (brpcm[4:1]). the brpcm[4:1] signals are available on these outputs when the backplane is configured for single-rail output. each brpcm[x] signal contains the recovered data stream passed through the elst block, and the sigx block. when the elst is not by-passed or the rclkosel register bit is not set, the brpcm[x] stream is aligned to the backplane timing and is updated on the falling edge of the associated brclk. when the elst is by-passed or the rclkosel register bit is set, brpcm[x] is aligned to the receive line timing and is updated on the falling edge of the associated rclko[x]. brdp[1] brdp[2] brdp[3] brdp[4] backplane receive positive line pulse (brdp[4:1]). the brdp[4:1] signals are available on these outputs when the backplane is configured for dual-rail output. each brdp[x] nrz output represents the rz receive digital positive pulse signal extracted from the input bipolar signal. brdp[x] is updated on the falling edge of the associated rclko[x]. mrd output 59 multiplexed receive data (mrd). when the multiplex enable (menb) input is asserted low, the four sets of pcm and signaling streams are bit interleaved into a single 16.384 mbit/s serial stream presented on mrd aligned with mrfpi. mrfpi is sampled on the rising edge of mrclk and mrd is updated on the falling edge of mrclk. when menb input is deasserted high, each pcm and signaling stream has its own dedicated pin and mrd is unused.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 17 pin name type pin no. function brsig[1] brsig[2] brsig[3] brsig[4] output 99 100 101 102 backplane receive signaling (brsig[4:1]). the brsig[4:1] signals are available on these outputs when the backplane is configured for single-rail output. each brsig[x] contains the extracted signaling bits for each channel in the frame, repeated for the entire superframe. each channel's signaling bits are valid in bit locations 5,6,7,8 of the channel and are channel- aligned with the brpcm[x] data stream. when the elst is not by-passed or the rclkosel register bit is not set, the brsig[x] stream is aligned to the backplane timing and is updated on the falling edge of brclk. when the elst is by-passed or the rclkosel register bit is set, brsig[x] is aligned to the receive line timing and is updated on the falling edge of the associated rclko[x]. brdn[1] brdn[2] brdn[3] brdn[4] backplane receive negative line pulse (brdn[4:1]). the brdn[4:1] signals are available on these outputs when the backplane is configured for dual-rail output. each brdn[x] nrz output represents the rz receive digital negative pulse signal extracted from the input bipolar signal. brdn[x] is updated on the falling edge of the associated rclko[x].
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 18 pin name type pin no. function brfpo[1] brfpo[2] brfpo[3] brfpo[4] output 95 96 97 98 backplane frame pulse output (brfpo[4:1]). when the equad is configured for backplane receive frame pulse output, each brfpo[x] pulses high for 1 brclk cycle (or 1 rclko[x] cycle if elst is by-passed or the rclkosel register bit is set) during bit 1 of each 256- bit frame, indicating the frame alignment of the brpcm[x] data stream. when configured for backplane receive signaling multiframe output, brfpo[x] pulses high for 1 brclk cycle (or 1 rclko[x] cycle if elst is by-passed) during bit 1 of frame 1 of the 16 frame signaling multiframe, indicating the signaling multiframe alignment of the brpcm[x] data stream. (even when signaling multiframing is disabled, the brfpo[x] output continues to indicate every 16 th frame.) when configured for backplane receive crc multiframe output, brfpo[x] pulses high for 1 brclk cycle (or 1 rclko[x] cycle if elst is by-passed) during bit 1 of frame 1 of every 16 frame crc multiframe, indicating the crc multiframe alignment of the brpcm[x] data stream. (even when crc multiframing is disabled, the brfpo[x] output continues to indicate the position of bit 1 of the fas frame every 16 th frame.) when configured for backplane receive composite multiframe output, brfpo[x] goes high on the falling brclk edge (or rclko[x] edge if elst is by-passed) marking the beginning of bit 1 of frame 1 of every 16 frame signaling multiframe, indicating the signaling multiframe alignment of the brpcm[x] data stream, and returns low on the falling brclk edge (or rclko[x] edge if elst is by-passed) marking the end of bit 1 of frame 1 of every 16 frame crc multiframe, indicating the crc multiframe alignment of the brpcm[x] data stream. in this mode both multiframe alignments can be decoded externally from the single brfpo[x] signal. if the signaling and crc multiframe alignments are coincident, brfpo[x] will pulse high for 1 clock cycle. when configured for backplane receive overhead output, brfpo[x] is high for timeslot 0 and timeslot 16 of each 256-bit frame, indicating the overhead bit positions of the brpcm[x] data stream. brfpo[x] is updated on the falling edge of the brclk or rclko[x].
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 19 pin name type pin no. function brclk input 94 backplane receive clock (brclk). when the multiplex enable (menb) input is deasserted high, brclk is a 2.048mhz clock with optional gapping for adaptation to non-uniform backplane data streams. brclk is common to all four framers. the equad may be configured to ignore the brclk input and use the rclko[x] signal in its place when the elst is bypassed or the rclkosel register bit is set. mrclk multiplex receive clock (mrclk). when the multiplex enable (menb) input is asserted low, mrclk is a 16.384 mhz clock. mrfpi is sampled on the rising edge of mrclk and mrd is updated on the rising edge of mrclk. the multiplexed bus can not be used if the elst is bypassed or the rclkosel register bit is set. brfpi input 93 backplane frame pulse input (brfpi). when the multiplex enable (menb) input is deasserted high, this input is used to frame align the received data to the system backplane. brfpi is common to all four framers. if frame alignment only is required, a pulse at least 1 brclk cycle wide must be provided on each brfpi every 256 bit periods. mrfpi multiplexed frame pulse input (mrfpi). when the multiplex enable (menb) input is asserted low, this input aligns all four sets of pcm and signaling streams to allow bit interleaved multiplexing. if frame alignment only is required, a pulse no more than 1 mrclk cycle wide must be provided on each mrfpi every 2048 bit periods.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 20 pin name type pin no. function btpcm[1] btpcm[2] btpcm[3] btpcm[4]/ input 61 62 63 64 backplane transmit pcm (btpcm[4:1]). the non- return to zero, digital data streams to be transmitted are input on these pins when the backplane is configured for non-multiplexed single-rail input. the btpcm[x] signal is sampled on the rising edge of the associated btclk[x]. btdp[1] btdp[2] btdp[3] btdp[4] backplane transmit positive line pulse (btdp[4:1]). the positive pulse of the dual-rail signals to be transmitted is input on these pins when the backplane is configured for non-multiplexed dual-rail input. in dual- rail input mode, the btdp[x] input by-passes the transmitter and is fed directly into the djat. btdp[x] is sampled on the rising edge of the associated btclk[x]. mtd multiplexed transmit data (mtd). mtd shares a pin with btpcm[1]. btpcm[4:2] are unused when the multiplex enable (menb) input is asserted low. when the multiplex enable (menb) input is asserted low, the four sets of pcm and signaling streams are expected in a single bit interleaved 16.384 mbit/s serial stream. frame alignment is indicated by mtfp. mtd is sampled on the rising edge of mtclk. btsig[1] btsig[2] btsig[3] btsig[4] input 65 66 67 68 backplane transmit signaling (btsig[4:1]). the btsig[4:1] input signals contain the signaling bits for each channel in the transmit data frame, repeated for the entire superframe. each signal is input on the btsig[x] pin when the backplane is configured for non- multiplexed single-rail input. each channel's signaling bits are in bit locations 5,6,7,8 of the channel and are channel-aligned with the btpcm[x] data stream. btsig[x] is sampled on the rising edge of the associated btclk[x]. if frame alignment is not required, btfp[x] may be tied to power or ground. btdn[1] btdn[2] btdn[3] btdn[4] backplane transmit negative line pulse (btdn[4:1]). the negative pulse of the dual-rail signal to be transmitted is input on these pins when the backplane is configured for non-multiplexed dual-rail input. in dual- rail input mode, the btdn[x] input by-passes the transmitter and is fed directly into the djat. btdn[x] is sampled on the rising edge of the associated btclk[x]. these inputs are unused when the multiplex enable (menb) input is asserted low.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 21 pin name type pin no. function btfp[1] btfp[2] btfp[3] btfp[4] input 69 70 71 72 backplane transmit frame pulse (btfp[4:1]). these inputs are used to frame align the transmitters to the system backplane. if basic frame alignment only is required, a pulse at least 1 btclk[x] cycle wide must be provided on btfp[x] at multiples of 256 bit periods. if multiframe alignment is required, transmit multiframe alignment must be enabled, and btfp[x] must be brought high to mark bit 1 of frame 1 of every 16 frame signaling multiframe and brought low following bit 1 of frame 1 of every 16 frame crc multiframe. this mode allows both multiframe alignments to be independently controlled using the single btfp[x] signal. note that if the signaling and crc multiframe alignments are coincident, btfp[x] must pulse high for 1 btclk[x] cycle every 16 frames. if register bit btfpref is set to logic 1, btfp[x] becomes the reference frame pulse for the associated interface. if frame alignment is not required, btfp[x] may be tied to logic high or low. mtfp multiplexed transmit frame pulse (mtfp). mtfp shares a pin with btfp[1]. btfp[4:2] are unused when the multiplex enable (menb) input is asserted low. when the multiplex enable (menb) input is asserted low, mtfp indicates the frame alignment of the bit interleaved pcm and signaling streams in the same way as btfp[x]. if basic frame alignment only is required, a pulse 1 mtclk cycle wide must be provided on mtfp at multiples of 2048 clock periods. if multiframe alignment is required, transmit multiframe alignment must be enabled, and mtfp must be brought high to mark bit 1 of frame 1 of the first multiplexed pcm stream (destined for transmitter number one) of every 16 frame signaling multiframe and brought low following bit 1 of frame 1 of the first multiplexed pcm stream of every 16 frame crc multiframe. this mode allows both multiframe alignments to be independently controlled using the single mtfp signal. all four interfaces will have the same frame alignment. note that if the signaling and crc multiframe alignments are coincident, mtfp must pulse high for 1 mtclk cycle every 16 frames (32768 clock cycles). mtfp is sampled on the rising edge of mtclk.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 22 pin name type pin no. function btclk[1] btclk[2] btclk[3] btclk[4] input 73 74 75 76 backplane transmit clock (btclk[4:1]). btclk[4:1] are the 2.048mhz transmit clocks with optional gapping for adaptation from non-uniform backplane data streams. the equad may be configured to ignore the btclk[x] input and use the associated rclko[x] signal in its place. mtclk multiplexed transmit clock (mtclk). mtclk shares a pin with btclk[1]. btclk[4:2] are unused when the multiplex enable (menb) input is asserted low. when the multiplex enable (menb) input is asserted low, this clock is 16.384 mhz. mtfp and mtd are sampled on the rising edge of mtclk. tdlsig[1] tdlsig[2] tdlsig[3] tdlsig[4]/ i/o 113 114 117 118 transmit data link signal (tdlsig[4:1]). the tdlsig[4:1] signals are input on this pin when the associated internal hdlc transmitter (xfdl) is disabled from use, or if fractional e1 insertion is selected. tdlsig[x] is the source for the data stream to be inserted into the selected data link bits. the equad may be configured to utilize timeslot 16 as a data link or utilize any combination of the national bits as a data link. if fractional e1 insertion is enabled, tdlsig[x] is the data source for the e1 channels enabled by the channel select registers. tdlsig[x] is sampled on the rising edge of the associated tdlclk[x]. the tdlsig[x] pins have integral pull-ups. tdlint[1] tdlint[2] tdlint[3] tdlint[4] transmit data link interrupt (tdlint[4:1]). the tdlint[4:1] signals are output on these pins when the associated xfdl is enabled. each tdlint[x] goes high when the last data byte written to the xfdl has been set up for transmission and processor intervention is required to either write control information to end the message, or to provide more data.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 23 pin name type pin no. function tdlclk[1] tdlclk[2] tdlclk[3] tdlclk[4]/ output 109 110 111 112 transmit data link clock (tdlclk[4:1]). the tdlclk[4:1] signals are available on this output when the associated internal hdlc transmitter (xfdl) is disabled from use, or if fractional e1 insertion is selected. the rising edge of tdlclk[x] is used to sample the data-link or fractional e1 data stream contained on the associated tdlsig[x] input. when the equad is not configured to transmit a data link and fractional e1 is disabled, the tdlclk[x] output is held low. tdludr[1] tdludr[2] tdludr[3] tdludr[4] transmit data link underrun (tdludr[4:1]). the tdludr[4:1] signals are available on this output when the associated xfdl is enabled. tdludr[x] goes high when the processor has failed to service the tdlint[x] interrupt before the transmit buffer is emptied. tclko[1] tclko[2] tclko[3] tclko[4] output 14 17 24 27 transmit clock output (tclko[4:1] ). the tdp[4:1], tdn[4:1], and tdd[4:1] outputs may be enabled to be updated on the rising or falling edge of the tclko[4:1] outputs. tclko[x] is a 2.048 mhz clock that is adequately jitter and wander free in absolute terms to permit an acceptable e1 signal to be generated. depending on the configuration of the equad, tclko[x] may be derived from tclki[x], rclko[x], or btclk[x], with or without jitter attenuation. tdp[1] tdp[2] tdp[3] tdp[4] / output 15 22 25 28 transmit digital positive line pulse (tdp[4:1]). these signals are available on the output when the equad is configured to transmit dual-rail data. the tdp[x] signal can be formatted for either rz or nrz waveforms, and can be enabled to be updated on the rising or falling edge of the associated tclko[x]. tdd[1] tdd[2] tdd[3] tdd[4] transmit digital data (tdd[4:1]). these signals are available on the output when configured to transmit single-rail data. the tdd[x] signal may be enabled to be updated on the rising or falling edge of the associated tclko[x].
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 24 pin name type pin no. function tdn[1] tdn[2] tdn[3] tdn[4] / output 16 23 26 29 transmit digital negative line pulse (tdn[4:1] ). these signals are available on the output when the equad is configured to transmit dual-rail data. the tdn[x] signal can be formatted for either rz or nrz waveforms, and can be enabled to be updated on the rising or falling edge of the associated tclko[x]. tflg[1] tflg[2] tflg[3] tflg[4] transmit fifo flag (tflg[4:1] ). these signals are available when configured to transmit single-rail data. the tflg[x] output indicates when the transmit rate conversion fifo in djat is nearing an empty or a full condition. either indication may be selected. this output may be enabled to be updated on the rising or falling edge of the associated tclko[x]. tclki[1] tclki[2] tclki[3] tclki[4] input 77 78 79 80 transmit clock input (tclki[x]). this input signal is used to generate the tclko[x] clock signal. depending upon the configuration of the equad, tclko[x] may be derived directly from tclki[x] by dividing tclki[x] by 8, or tclko[x] may be derived from tclki[x] after jitter attenuation. if tclki[x] is jitter-free when divided down to 8 khz, then it is possible to derive tclko[x] from tclki[x] when tclki[x] is a multiple of 8 khz (i.e. nx8 khz, for n equals 1 to 256). the equad may be configured to ignore the tclki[x] input and utilize btclk[x] or rclko[x] instead. rclko[x] is also substituted for tclki[x] if line loopback is enabled. xclk/ input 60 crystal clock input (xclk). this signal provides timing for many portions of the equad. depending on the configuration of the equad, xclk is nominally a 49.152 mhz or 16.384 mhz 50% duty cycle clock. when transmit clock generation or jitter attenuation is not required, xclk may be driven with a 16.384 mhz clock. when transmit clock generation or jitter attenuation is required, xclk must be driven with a 49.152 mhz clock. vclk vector clock (vclk). the vclk signal is used during equad production test to verify internal functionality. intb output 58 active low open-drain interrupt signal (intb). this signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources, including the internal hdlc transceiver. note that intb will remain low until all active, unmasked interrupt sources are acknowledged at their source.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 25 pin name type pin no. function csb input 44 active low chip select (csb). this signal must be low to enable equad register accesses. this signal must be toggled high to clear the pmctst register bit (register 00bh or 20bh) and to ensure the equad will operate in normal mode. d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] i/o 46 47 48 49 54 55 56 57 bi-directional data bus (d[7:0]). this bus is used during equad read and write accesses. rdb input 43 active low read enable (rdb). this signal is pulsed low to enable a equad register read access. the equad drives the d[7:0] bus with the contents of the addressed register while rdb and csb are both low. wrb input 42 active low write strobe (wrb). this signal is pulsed low to enable a equad register write access. the d[7:0] bus contents are clocked into the addressed normal mode register on the rising edge of wrb while csb is low. ale input 41 address latch enable (ale). this signal latches the address bus contents, a[9:0], when low, allowing the equad to be interfaced to a multiplexed address/data bus. when ale is high, the address latches are transparent. ale has an integral pull-up. rstb input 40 active low reset (rstb). this signal is set low to asynchronously reset the equad. rstb is a schmitt- trigger input with integral pull-up. a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] input 30 31 32 33 34 35 36 37 38 39 address bus (a[9:0]). this bus selects specific registers during equad register accesses.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 26 pin name type pin no. function pha[0] pha[1] pha[2] pha[3] pha[4] power 18 52 89 105 121 ac power pins (pha[4:0]). these pins must be connected to a common, well decoupled +5v dc supply together with the dc power pins phd[3:0] . phd[0] phd[1] phd[2] phd[3] power 20 50 85 115 dc power pins (phd[3:0]). these pins must be connected to a common, well decoupled +5v dc supply together with the ac power pins pha[4:0]. pla[0] pla[1] pla[2] pla[3] pla[4] pla[5] ground 19 53 90 106 122 1 ac ground pins (pla[5:0]). these pins must be connected to a common ground together with the dc ground pins pld[3:0]. pld[0] pld[1] pld[2] pld[3] ground 21 51 86 116 dc ground pins (pld[3:0]). these pins must be connected to a common ground together with the ac ground pins pla[5:0]. notes on pin description: 1. the pla[5:0] and pld[3:0] ground pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the device. the pha[4:0] and phd[3:0] power pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the device. these power supply connections must all be utilized and must all connect to a common +5 v or ground rail, as appropriate. 2. inputs menb, rstb and ale have integral pull-up resistors. 3. all outputs have 2 ma drive capability except for mrd and the d[7:0] bidirectionals which have 4 ma drive capability. 4. all inputs and bidirectionals present minimum capacitive loading and operate at ttl logic levels. 5. the tdlsig/tdlint[4:1] pins have integral pull-up resistors and default to being inputs after a reset.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 27 6. when an internal rfdl is enabled, the rdlint[x] output goes high: 1) when the number of bytes specified in the rfdl interrupt status/control register have been received on the data link, 2) immediately on detection of rfdl fifo buffer overrun, 3) immediately on detection of end of message, 4) immediately on detection of an abort condition, or, 5) immediately on detection of the transition from receiving all ones to flags. the interrupt is cleared at the start of the next rfdl data register read that results in an empty fifo buffer. this is independent of the fifo buffer fill level for which the interrupt is programmed. if there is still data remaining in the buffer, rdlint[x] will remain high. an interrupt due to a rfdl fifo buffer overrun condition is not cleared on a rfdl data register read but on a rfdl status register read. the rdlint[x] output can always be forced low by disabling the rfdl (setting the en bit in the rfdl configuration register to logic 0), or by forcing the rfdl to terminate reception (setting the tr bit in the rfdl configuration register to logic 1). the rdlint[x] output may be forced low by disabling the interrupts with the rfdl interrupt status/control register. however, the internal interrupt latch is not cleared, and the state of this latch can still be read through the rfdl interrupt status/control register. 7. the rdleom[x] output goes high: 1) immediately on detection of rfdl fifo buffer overrun, 2) when the data byte written into the rfdl fifo buffer due to an end of message condition is read, 3) when the data byte written into the rfdl fifo buffer due to an abort condition is read, or, 4) when the data byte written into the rfdl fifo buffer due to the transition from receiving all ones to flags is read. rdleom[x] is set low by reading the associated rfdl status register or by disabling the rfdl.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 28 8. the tdludr[x] output goes high when the processor is unable to service the tdlint[x] request for more data before a specific time-out period. this period is dependent upon the frequency of tdlclk[x]: 1) for a tdlclk[x] frequency of 4 khz, the time-out is 1.0 ms; 2) for a tdlclk[x] frequency of 20 khz, the time-out is 0.2 ms; 3) for a tdlclk[x] frequency of 64 khz, the time-out is 62.5 s.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 29 8 functional description 8.1 digital receive interface (drif) the digital e1 receive interface provides control over the various input options available on the multifunctional digital receive pins rdp/rdd[x] and rdn/rlcv[x]. when configured for dual-rail input, the multifunctional pins become the rdp[x] and rdn[x] inputs. these inputs can be enabled to receive either return-to-zero (rz) or non-return-to-zero (nrz) signals; the nrz input signals can be sampled on either the rising or falling edge of rclki[x]. when the interface is configured for single-rail input, the multifunctional pins become the rdd[x] and rlcv[x] inputs, which can be sampled on either the rising or falling rclki[x] edge. 8.2 clock and data recovery (cdrc) the clock and data recovery function is provided by a data and clock recovery (cdrc) block that provides clock and pcm data recovery, hdb3 decoding, bipolar violation detection, and loss of signal detection. the cdrc block recovers the clock from the incoming rz data pulses using a digital phase- locked-loop and recovers the nrz data. loss of signal is indicated after exceeding a programmed threshold of 10, 15, 31, 63 or 175 consecutive bit periods of the absence of pulses on both the positive and negative line pulse inputs and is cleared after the occurrence of a single line pulse. an alternate loss of signal indication is provided which is cleared only after 255 bit periods during which no sequence of four consecutive zeros has been received. if enabled, a microprocessor interrupt is generated when a loss of signal is detected and when the signal returns. the hdb3 decoding is summarized as follows: if a bipolar violation (bpv) preceded by two zeros is received, the violation and the preceding three bit periods are decoded as four zeros. if ami line code is selected, no substitution is made. if hdb3 line code is selected, a line code violation is declared if any bipolar violation is of the same polarity as the previous bpv or if the bpv is not preceded by two spaces (the second criteria is maskable). if ami line code is selected, all bipolar violations are counted as line code violations. the input jitter tolerance for e1 interfaces complies with itu-t recommendation g.823. the tolerance is measured with a 2 15 -1 sequence. the e1 jitter tolerance is with algsel set to 1 and to 0 is shown in figure 2 and figure 3.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 30 figure 2 - cdrc jitter tolerance with algsel = 1 jitter frequency (hz) . 0.01 0.1 jitter amplitude (uip-p) 1.0 10 measured cdrc jitter tolerance (algsel = 1) g823 jitter tolerance specification measurement limit 100 1k 10k 100k . 10
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 31 figure 3 - cdrc jitter tolerance with algsel = 0 . measurement limit measured cdrc jitter tolerance (algsel = 0) g823 jitter tolerance specification 0.01 0.1 jitter amplitude (uip-p) 1.0 10 jitter frequence (hz) 100 1k 10k 100k . 10 8.3 framer (frmr) the framer (frmr) block searches for frame alignment, crc multiframe alignment, and channel associated signaling (cas) multiframe alignment in the incoming recovered pcm stream. once the frmr has found basic (or fas) frame alignment, the incoming pcm data is continuously monitored for fas/nfas framing bit errors. framing bit errors are accumulated in the framing bit error counter contained in the pmon block. once the frmr has found cas multiframe alignment, the pcm data is continuously monitored for cas multiframe alignment pattern errors. once the
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 32 frmr has found crc multiframe alignment, the pcm data is continuously monitored for crc multiframe alignment pattern errors, and crc-4 errors. the frmr also detects and indicates loss of frame, loss of cas multiframe, and loss of crc multiframe, based on user-selectable criteria. the reframe operation can be initiated by software (via the frmr frame alignment options register), by excessive crc errors, or when crc multiframe alignment is not found within 8 ms. the frmr also identifies the position of the frame, the cas multiframe, and the crc multiframe. the frmr extracts timeslot 16 for optional use as a data link and also extracts the contents of the international bits (from both the fas frames and the nfas frames), the national bits, and the extra bits (from timeslot 16 of frame 0 of the cas multiframe), and stores them in the frmr international/national bits register, and the frmr extra bits register respectively. the frmr identifies the raw bit values for the remote (or distant frame) alarm (bit 3 in timeslot 0 of nfas frames) and the remote signaling multiframe (or distant multiframe) alarm (bit 6 of timeslot 16 of frame 0 of the cas multiframe) via the frmr international/national bits register, and the frmr extra bits register respectively. access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 2 or 3 consecutive occurrences, as per recommendation o.162. detection of ais and timeslot 16 ais are provided; ais is also integrated and an ais alarm is indicated if the ais condition has persisted for at least 100 ms. the out of frame (oof=1) condition is also integrated, indicating a red alarm if the oof condition has persisted for at least 100 ms. an interrupt may be generated to signal a change in the state of any status bits (oof, oosmf, oocmf, ais, or red), and to signal when any event (rra, rrma, aisd, t16aisd, cofa, fer, smfer, cmfer, crce, or febe) has occurred. frame find the frame find block searches for frame alignment using one of two user- selectable algorithms, as defined in recommendation g.706. optionally, a two frame check sequence can be added to either algorithm to provide protection against false frame alignment in the presence of random mimic patterns. the first algorithm finds frame alignment by using the following sequence: 1. search for the presence of the correct 7-bit fas;
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 33 2. check that the fas is absent in the following frame by verifying that bit 2 of the assumed timeslot 0 byte is a logic 1; 3. check that the correct 7-bit fas is present in the assumed timeslot 0 byte of the next frame. if either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the errored timeslot 0 byte location. the second algorithm is similar to the first, but adds a one frame "hold-off" in step 2 to begin a new search in the bit immediately following the second 7-bit fas that is checked. this "hold-off" is performed only after the condition in step 2 fails, providing a more robust algorithm which allows the framer to operate correctly in the presence of fixed timeslot data imitating the fas pattern. a check sequence can be added to either algorithm to verify correct frame alignment in the presence of random imitative fass. note that this check sequence should be enabled when monitoring an unframed 2 15 -1 pseudo random sequence to avoid framing to the single mimic framing pattern contained in the sequence. the check consists of verifying correct frame alignment for an additional two frames, as follows: 1. once frame alignment (in frame "n") is determined, check that the fas is absent in the following frame (frame "n+1") by verifying that bit 2 of timeslot 0 is a logic 1; 2. then, check that the correct 7-bit fas is present in timeslot 0 of the next frame (frame "n+2"). if either of the two conditions in the check sequence are not met, a new search for frame alignment is initiated in the bit immediately following the errored byte location when using the first algorithm, and is initiated in the bit immediately following the byte location in frame "n+2" when using the second algorithm. these algorithms are illustrated in figure 4.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 34 figure 4 - basic framing algorithm flowchart out of frame synchronization search for 7-bit fas pattern check if bit 2=1 in current byte loc. of next frame check occurrence of 7-bit fas in next frame not found found algorithm #1: bit 2=0 wait for byte location in next frame bit 2=1 algorithm #2: bit 2 =0 2nd fas not found fas found & check sequence selected frame alignment established check bit 2 =1 in following frame check occurrence of 7-bit fas in next frame algorithm #1: bit 2=0 bit 2=1 algorithm #2: bit 2 =0 fas not found fas found frame alignment established fas found & no check sequence selected
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 35 these algorithms provide robust framing operation even in the presence of random bit errors: framing with algorithm #1 or #2 provides a 99.98% probability of finding frame alignment within 1 ms in the presence of 10 -3 bit error rate and no mimic patterns. once frame alignment is found, the block sets the oof indication low, indicates a change of frame alignment (if it occurred), and monitors the frame alignment signal, indicating errors occurring in the 7-bit fas pattern and in bit 2 of nfas frames, and indicating the debounced value of the remote alarm bit (bit 3 of nfas frames). using debounce, the remote alarm bit has <0.00001% probability of being falsely indicated in the presence of a 10 -3 bit error rate. the block declares loss of frame alignment if 3 or 4 consecutive fass have been received in error or, additionally, if bit 2 of nfas frames has been in error for 3 consecutive occasions. in the presence of a random 10 -3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of >12 minutes. the frame find block can be forced to initiate a frame search at any time when any of the following conditions are met: the software re-frame bit (refr) in the frame alignment options register changes from logic 0 to logic 1; the crc frame find block is unable to find crc multiframe alignment; or the crc frame find block accumulates excessive crc evaluation errors ( 3 915 crc errors in 1 second) and is enabled to force a re-frame. crc frame find once the basic frame alignment has been found, the crc frame find block searches for crc multiframe alignment by observing whether the international bits (bit 1 of timeslot 0) of nfas frames follow the crc multiframe alignment pattern. multiframe alignment is declared if at least two valid crc multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms. once crc multiframe alignment is found, the block sets the oocmf indication low, and monitors the multiframe alignment signal, indicating errors occurring in the 6-bit pattern, and indicating the value of the febe bits (bit 1 of frames 13 and 15 of the multiframe).the block declares loss of crc multiframe alignment if four consecutive crc multiframe alignment signals have been received in error, or if frame alignment has been lost.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 36 the crc frame find block will force the frame find block to initiate a basic frame search when crc multiframe alignment has not been found for 8 ms. crc check and ais detection the crc check and ais detect block computes the 4-bit crc checksum for each incoming sub-multiframe and compares this 4-bit result to the received crc remainder bits in the subsequent sub-multiframe. the block also accumulates crc errors over 1 second intervals, monitoring for excessive crc errors and optionally, forcing the frame find block to initiate a frame search when ? 915 crc errors occur in 1 second. the number of crc errors accumulated during the previous second is available by reading the frmr crc error counter registers. the block also detects the occurrence of an unframed all-ones receive data stream, indicating the ais by setting the aisd indication when less than 3 zero bits are received in 2 frames (512 consecutive bits); the aisd indication is reset when 3 or more zeros in the e1 stream are observed, or when frame alignment is found. signaling frame find once the basic frame alignment has been found, the signaling frame find block searches for cas multiframe alignment using one of two user-selectable algorithms, one of which is compatible with recommendation g.732. once frame alignment has been found, the first algorithm monitors timeslot 16 of each frame; it declares cas multiframe alignment when 15 consecutive frames with bits 1-4 of timeslot 16 not containing the alignment pattern are observed to precede a frame with timeslot 16 containing the correct alignment pattern. the second algorithm, compatible with g.732, also monitors timeslot 16 of each frame, and declares cas multiframe alignment when non-zero bits 1-4 of timeslot 16 are observed to precede a timeslot 16 containing the correct alignment pattern. once cas multiframe alignment has been found, the block sets the oosmf indication to logic 0, and monitors the cas multiframe alignment signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the remote signaling multiframe alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). using debounce, the remote signaling multiframe alarm bit has < 0.00001% probability of being falsely indicated in the presence of a 10 -3 bit error rate. this block also indicates the reception of timeslot 16 ais when timeslot 16 has been all-ones for two consecutive frames while out of cas multiframe. the block declares loss of cas multiframe alignment if two
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 37 consecutive cas multiframe alignment signals have been received in error, or additionally, if all the bits in timeslot 16 are logic 0 for 1 or 2 (selectable) cas multiframes. loss of cas multiframe alignment is also declared if frame alignment has been lost. alarm integration the alarm integrator block monitors the oof and the ais indications, verifying that each condition has persisted for 104 ms (6 ms) before indicating the alarm condition. the alarm is removed when the condition has been absent for 104 ms (6 ms). the ais alarm algorithm accumulates the occurrences of aisd (ais detection). aisd is defined as an unframed pattern with less than 3 zeros in two consecutive frame times (512 bits). the alarm integrator block counts the occurrences of aisd over a 4 ms interval and indicates a valid ais presence when 13 or more aisd indications (of a possible 16) have been received. each interval with a valid ais presence indication increments an interval counter which declares ais alarm when 25 valid intervals have been accumulated. an interval with no valid ais presence indication decrements the interval counter; the ais alarm declaration is removed when the counter reaches 0. this algorithm provides a 99.8% probability of declaring an ais alarm within 104 ms in the presence of a 10 -3 mean bit error rate. the ts16 ais alarm algorithm accumulates the occurrences of ts16aisd (ts16 ais detection). ts16aisd is defined as two consecutive all ones time slot 16 bytes while out of signaling multiframe. each interval with a valid ts16 ais presence indication increments an interval counter which declares ts16 ais alarm when 22 valid intervals have been accumulated. an interval with no valid ts16 ais presence indication decrements the interval counter; the ts16 ais alarm declaration is removed when the counter reaches 0. this algorithm provides a 99.1% probability of declaring an ts16 ais alarm within 3.1 ms after loss of signaling multiframe detection in the presence of a 10 -3 mean bit error rate. the red alarm algorithm monitors occurrences of oof over a 4 ms interval, indicating a valid oof interval when one or more oof indications occurred during the interval, and indicating a valid in frame (inf) interval when no oof indication occurred for the entire interval. each interval with a valid oof indication increments an interval counter which declares red alarm when 25 valid intervals have been accumulated. an interval with valid inf indication decrements the interval counter; the red alarm declaration is removed when the
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 38 counter reaches 0. this algorithm biases oof occurrences, leading to declaration of red alarm when intermittent loss of frame alignment occurs. 8.4 performance monitor counters (pmon) the performance monitor counters function is provided by the performance monitor (pmon) block that accumulates crc error events, frame synchronization bit error events, line code violation events, and far end block error events with saturating counters over consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). when the transfer clock signal is applied, the pmon block transfers the counter values into holding registers and resets the counters to begin accumulating events for the interval. the counters are reset in such a manner that error events occurring during the reset are not missed. if enabled, an interrupt is generated whenever counter data is transferred into the holding registers. if the holding registers are not read between successive transfer clocks, an overrun register bit is asserted. generation of the transfer clock within the equad chip is performed by writing to any counter register location (x4ah to x4fh) or by writing to the equad revision/chip id/global pmon update register (00ch). the holding register addresses are contiguous to facilitate polling operations. 8.5 hdlc receiver (rfdl) the hdlc receiver function is provided by the rfdl block. the rfdl is a microprocessor peripheral used to receive lapd/hdlc frames on either time slot 16 or the national use bits of time slot 0. the rfdl detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives frame data, and calculates the crc q.921 frame check sequence (fcs). received data is placed into a 4-level fifo buffer. the status register contains bits which indicate overrun, end of message, flag detected, and buffered data available. on end of message, the status register also indicates the fcs status and the number of valid bits in the final data byte. interrupts are generated when one, two or three bytes (programmable via the rfdl configuration register) are stored in the fifo buffer. interrupts are also generated when the terminating flag sequence, abort sequence, or fifo buffer overrun are detected.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 39 when the internal hdlc receiver is disabled, the serial data extracted by the frmr block is output on the rdlsig[x] pin and is updated on the falling clock edge of the rdlclk[x] pin. 8.6 elastic store (elst) the elastic store function is provided by the elst block. the elastic store (elst) block synchronizes incoming pcm frames to the local backplane clock, brclk. the frame data is buffered in a two frame circular data buffer. input data is written to the buffer using a write pointer and output data is read from the buffer using a read pointer. when the backplane timing is derived from the receive line data (i.e. the rclko[x[ output is used), the elastic store can be bypassed to eliminate the 2 frame delay. in this configuration the elastic store can be used to measure frequency differences between the recovered line clock and another 2.048 mhz clock applied to the brclk input. a typical example might be to measure the difference in frequency between two received e1 streams (i.e. east-west frequency difference) by monitoring the number of slip occurrences of one direction with respect to the other. when the elastic store is being used, if the average frequency of the incoming data is greater than the average frequency of the backplane clock, the write pointer will catch up to the read pointer and the buffer will be filled. under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. the following frame of pcm data will be deleted. if the average frequency of the incoming data is less than the average frequency of the backplane clock, the read pointer will catch up to the write pointer and the buffer will be empty. under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. the last frame which was read will be repeated. a slip operation is always performed on a frame boundary. to allow for the extraction of signaling information in the pcm data timeslots, multiframe identification is also passed through the elst. 8.7 signaling extractor (sigx) the signaling extraction function is provided by the signaling extractor (sigx) block. the block provides channel associated signaling (cas) extraction from an e1 signaling multiframe. signaling data is extracted from timeslot 16 of each
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 40 frame within a signaling multiframe and buffered. the sigx selectively debounces the bits, and serializes the results onto the 2048 kbit/s serial stream brsig[x] output. buffered signaling data is aligned with its associated voice timeslot in the e1 frame. the sigx provides user control over signaling freezing with a 95% confidence level of freezing with valid signaling data for a 50% ones density out-of-frame condition. the sigx also provides control over timeslot data inversion, trunk conditioning, and signaling debounce on a per-timeslot basis directly, via the microprocessor interface (mpif). 8.8 backplane receive interface (brif) the backplane receive interface allows data to be presented to a backplane in either a 2.048 mbit/s or a 16.384 mbit/s serial stream and allows bpv transparency by outputting dual-rail data at 2.048 mbit/s. the block generates the output data stream on the brpcm[x] pin containing 32 timeslot bytes of data. the brsig[x] output pin contains 30 bytes of signaling nibble data located in the least significant nibble of each byte. the framing alignment indication on the brfpo[x] pin can be configured to indicate the first bit of each 256-bit frame, the first bit of the first frame of the crc multiframe, the first bit of the first frame of the signaling multiframe or all overhead bits. when configured for a multiplexed backplane, the four sets of pcm and signaling streams are bit interleaved into a 16.384 mbit/s serial stream. the mrfpi pin must go to logic "1" for one mrclk cycle to indicate the alignment of the first pcm bit of the frame or multiframe from receiver number one. 8.9 transmitter (tran) the transmitter function is provided by the tran block. the tran generates a 2048 kbit/s data stream according to itu-t recommendations, providing individual enables for frame generation, crc multiframe generation, and channel associated signaling (cas) multiframe generation. in concert with transmit per-channel serial controller (tpsc), the tran block provides per-timeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of the signaling source and cas data. all timeslots can be forced into a trunk conditioning state (idle code substitution and
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 41 signaling substitution) by use of the master trunk conditioning bit in the configuration register. common channel signaling (ccs) is supported in time slot 16 either through the internal hdlc transmitter (xfdl) or through a serial data input and clock output. support is provided for the transmission of ais and ts16 ais, and the transmission of remote alarm and remote multiframe alarm signals. pcm output signals may be selected to conform to hdb3 or ami line coding. 8.10 transmit per-channel serial controller (pcsc) the transmit per-channel serial controller allows data and signaling trunk conditioning or idle code to be applied on the transmit e1 stream on a per- timeslot basis. it also allows per-timeslot control of data inversion and application of digital milliwatt. the transmit per-channel serial controller function is provided by a per-channel serial controller (pcsc) block. the tpsc interfaces directly to the tran block and provides serial streams for signaling control, idle code data and pcm data control. the registers are accessible from the p interface in an indirect address mode. the busy indication signal can be polled from an internal status register to check for completion of the current operation. 8.11 hdlc transmitter (xfdl) the hdlc transmitter function is provided by the xfdl block. the xfdl is designed to provide a serial data link for the tran e1 transmitter block. the xfdl is used under microprocessor or dma control to transmit hdlc data frames in time slot 16 or in the time slot 0 national use bits when the equad is enabled to use the internal hdlc transmitter. the xfdl performs all of the data serialization, crc generation, zero-bit stuffing, as well as flag, idle, and abort sequence insertion. data to be transmitted is provided on an interrupt- driven basis by writing to a double-buffered transmit data register. upon completion of the frames, a crc q.921 frame check sequence is transmitted, followed by idle flag sequences. if the transmit data register underflows, an abort sequence is automatically transmitted. when enabled for use (via the en bit in the xfdl configuration register), the xfdl continuously transmits the flag character (01111110). data bytes to be transmitted are written into the transmit data register. after the parallel-to-serial
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 42 conversion of each data byte, an interrupt is generated to signal the controller to write the next byte into the transmit data register. after the last data frame byte is transmitted, the crc word (if crc insertion has been enabled), or a flag (if crc insertion has not been enabled) is transmitted. the xfdl then returns to the transmission of flag characters. if there are more than five consecutive ones in the raw transmit data or in the crc data, a zero is stuffed into the serial data output. this prevents the unintentional transmission of flag or abort characters. abort characters can be continuously transmitted at any time by setting a control bit. during transmission, an underrun situation can occur if data is not written to the transmit data register before the previous byte has been depleted. in this case, an abort sequence is transmitted, and the controlling processor is notified via the tdludr signal. optionally, the interrupt and underrun signals can be independently enabled to also generate an interrupt on the intb output, providing a means to notify the controlling processor of changes in the xfdl operating status. when the internal hdlc transmitter is disabled, the serial data to be transmitted on data link can be input on the tdlsig pin timed to the clock rate output on the tdlclk pin. 8.12 digital jitter attenuator (djat) the digital jitter attenuation function is provided by the digital jitter attenuator (djat) block. the djat block receives jittered e1 data in nrz format from tran on two separate inputs, which allows bipolar violations to pass through the block uncorrected. the incoming data streams are stored in a fifo timed to the transmit clock (either btclk[x] or rclko[x]). the respective input data emerges from the fifo timed to the jitter attenuated clock (tclko[x]) referenced to either tclki[x], btclk[x], or rclko[x]. the jitter attenuator generates the jitter-free 2.048 mhz tclko[x] output transmit clock by adaptively dividing the 49.152 mhz xclk signal according to the phase difference between the generated tclko[x] and input data clock to djat (either btclk[x] or rclko[x]). fluctuations in the phase of the input data clock are attenuated by the phase-locked loop within djat so that the frequency of tclko[x] is equal to the average frequency of the input data clock. phase fluctuations with a jitter frequency above 8.8 hz are attenuated by 6 db per octave of jitter frequency. wandering phase fluctuations with frequencies below 8.8 hz are tracked by the generated tclko[x]. to provide a smooth flow of data out of djat, tclko[x] is used to read data out of the fifo.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 43 if the fifo read pointer (timed to tclko[x]) comes within one bit of the write pointer (timed to the input data clock, btclk[x] or rclko[x]), djat will track the jitter of the input clock. this permits the phase jitter to pass through unattenuated, inhibiting the loss of data. jitter characteristics the djat block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. it can accommodate up to 35 uipp of input jitter at jitter frequencies above 9 hz. for jitter frequencies below 9 hz, more correctly called wander, the tolerance increases 20 db per decade. in most applications the djat block will limit jitter tolerance at lower jitter frequencies only. for high frequency jitter, above 10 khz for example, other factors such as the clock and data recovery circuitry may limit jitter tolerance and must be considered. for low frequency wander, below 10 hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. the djat block meets the low frequency jitter tolerance requirements of itu-t recommendation g.823. djat exhibits negligible jitter gain for jitter frequencies below 8.8 hz, and attenuates jitter at frequencies above 8.8 hz by 20 db per decade. in most applications the djat block will determine jitter attenuation for higher jitter frequencies only. wander, below 10 hz for example, will essentially be passed unattenuated through djat. jitter, above 10 hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the generated residual jitter of in cases where incoming jitter is insignificant. this generated residual jitter is directly related to the use of 24x (49.152 mhz) digital phase locked loop for transmit clock generation. djat meets the jitter attenuation requirements of the itu-t recommendations g.737, g.738, g.739 and g.742. jitter tolerance jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. for djat, the input jitter tolerance is 35 unit intervals peak-to-peak (uipp) with a worst case frequency offset of 308 hz. it is 48 uipp with no frequency offset. the frequency offset is the difference between the frequency of xclk divided by 24 and that of the input data clock.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 44 figure 5 - djat jitter tolerance the accuracy of the xclk frequency and that of the djat pll reference input clock used to generate the jitter-free tclko[x] have an effect on the minimum jitter tolerance. given that the djat pll reference clock accuracy can be 103 hz from 2.048 mhz, and that the xclk input accuracy can be 100 ppm from 49.152 mhz, the minimum jitter tolerance for various differences between the frequency of pll reference clock and xclk/24 are shown in figure 6.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 45 figure 6 - djat minimum jitter tolerance vs. xclk accuracy 100 200 300 308 djat minimum jitter tolerance ui pp 45 40 35 30 0 100 49 max frequency offset (pll ref to xclk) xclk accuracy hz ppm 34.9 39 42.4 jitter transfer the output jitter for jitter frequencies from 0 to 8.8 hz is no more than 0.1 db greater than the input jitter, excluding the residual jitter. jitter frequencies above 8.8 hz are attenuated at a level of 6 db per octave, as shown in figure 7.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 46 figure 7 - djat jitter transfer 0 -10 -20 -30 -40 -50 1 10 100 1k 10k jitter frequency, hz jitter gain (db) 8.8 g.737, g738, g.739, g.742 max djat response frequency range in the non-attenuating mode, that is, when the fifo is within one ui of overrunning or under running, the tracking range is 1.963 to 2.133 mhz. the guaranteed linear operating range for the jittered input clock is 2.048 mhz 1278 hz with worst case jitter (42 uipp) and maximum xclk frequency offset ( 100 ppm). the nominal range is 2.048 mhz 103 hz with no jitter or xclk frequency offset. 8.13 timing options (tops) the timing options block provides a means of selecting the source of the internal input clock to the djat block, the reference signal for the digital pll, and the clock source used to derive the output tclko[x] signal. 8.14 digital e1 transmit interface (dtif) the digital e1 transmit interface provides control over the various output options available on the multifunctional digital transmit pins tdp/tdd[x] and tdn/tflg[x]. when configured for dual-rail output, the multifunctional pins become the tdp[x] and tdn[x] outputs. these outputs can be formatted as either return-to-zero (rz) or non-return-to-zero (nrz) signals and can be
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 47 updated on either the rising or falling edge of tclko[x]. when the interface is configured for single-rail output, the multifunctional pins become the tdd[x] and tflg[x] outputs, which can be enabled to be updated on either the rising or falling tclko[x] edge. further, the tflg[x] output can be enabled to indicate fifo empty or fifo full status. the dtif block also provides alarm indication signaling (ais) generation capability by generating alternating mark signals on the tdp/tdn[x] outputs, or all-ones on the tdd[x] output, when the taisen bit is set in the transmit e1 interface configuration register. this is useful when the internal loopback modes are used. 8.15 backplane transmit interface (btif) the backplane transmit interface allows data to be taken from a backplane in either a 2.048 mbit/s or 16.384 mbit/s serial stream and allows bpv transparency by accepting dual-rail data input at 2.048 mbit/s. when configured to receive a 2.048 mbit/s data rate stream, the block expects the input data stream on the btpcm[x] pin to contain 32 timeslots. the btsig[x] input pin must contain 30 bytes of signaling nibble data located in the least significant nibble of each byte. the framing alignment indication on the btfp[x] pin indicates the framing bit position of the 256-bit frame (or, optionally, the framing bit position of the first frame of the signaling multiframe frame, and the crc multiframe). when configured to interface to a 16.384 mbit/s serial stream, the four sets of pcm and signaling streams are expected to be bit interleaved. the mtfp pin marks the framing bit position of the first multiplexed pcm stream (destined for transmitter number one) or, optionally, the framing bit position of the first frame of the signaling multiframe frame, and the crc multiframe. mtfp operates in a similar fashion to btfp[x], but is only valid at positions coincident with the first multiplexed pcm stream. all four multiplexed interfaces will have the same frame, signaling multiframe, and crc multiframe alignment. see the functional timing section for more details. 8.16 microprocessor interface (mpif) the microprocessor interface allows the equad to be configured, controlled and monitored via internal registers.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 48 9 register description table 1 - normal mode register memory map address register #1 # 2 # 3 # 4 000h 080h 100h 180h receive options 001h 081h 101h 181h receive backplane options 002h 082h 102h 182h datalink options 003h 083h 103h 183h receive interface configuration 004h 084h 104h 184h transmit interface configuration 005h 085h 105h 185h transmit backplane options 006h 086h 106h 186h transmit framing and bypass options 007h 087h 107h 187h transmit timing options 008h 088h 108h 188h master interrupt source 009h 089h 109h 189h receive ts0 data link enables 00ah 08ah 10ah 18ah master diagnostics 00bh equad master test 00ch equad revision/chip id/global pmon update 08bh 10bh 18bh reserved 08ch 10ch 18ch reserved 00dh 08dh 10dh 18dh framer reset 00eh 08eh 10eh 18eh phase status word (lsb) 00fh 08fh 10fh 18fh phase status word (msb) 010h 090h 110h 190h cdrc configuration 011h 091h 111h 191h cdrc interrupt enable 012h 092h 112h 192h cdrc interrupt status 013h 093h 113h 193h alternate loss of signal
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 49 address register #1 # 2 # 3 # 4 014h 094h 114h 194h channel select (1 to 8) 015h 095h 115h 195h channel select (9 to 16) 016h 096h 116h 196h channel select (17 to 24) 017h 097h 117h 197h channel select (25 to 32) 018h 098h 118h 198h djat interrupt status 019h 099h 119h 199h djat reference clock divisor (n1) control 01ah 09ah 11ah 19ah djat output clock divisor (n2) control 01bh 09bh 11bh 19bh djat configuration 01ch 09ch 11ch 19ch elst configuration 01dh 09dh 11dh 19dh elst interrupt enable/status 01eh 09eh 11eh 19eh elst idle code 01fh 09fh 11fh 19fh elst reserved 020h 0a0h 120h 1a0h frmr framing alignment options 021h 0a1h 121h 1a1h frmr frmr maintenance mode options 022h 0a2h 122h 1a2h frmr framing status interrupt enable 023h 0a3h 123h 1a3h frmr maintenance/alarm status interrupt enable 024h 0a4h 124h 1a4h frmr framing status interrupt indication 025h 0a5h 125h 1a5h frmr maintenance/alarm status interrupt indication 026h 0a6h 126h 1a6h frmr framing status 027h 0a7h 127h 1a7h frmr maintenance/alarm status 028h 0a8h 128h 1a8h frmr international/national bits 029h 0a9h 129h 1a9h frmr extra bits 02ah 0aah 12ah 1aah frmr crc error count - lsb
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 50 address register #1 # 2 # 3 # 4 02bh 0abh 12bh 1abh frmr crc error count - msb 02ch 0ach 12ch 1ach ts16 ais alarm status 02dh 0adh 12dh 1adh reserved 02eh 0aeh 12eh 1aeh reserved 02fh 0afh 12fh 1afh reserved 030h 0b0h 130h 1b0h tpsc configuration 031h 0b1h 131h 1b1h tpsc p access status 032h 0b2h 132h 1b2h tpsc timeslot indirect address/control 033h 0b3h 133h 1b3h tpsc timeslot indirect data buffer 034h 0b4h 134h 1b4h xfdl configuration 035h 0b5h 135h 1b5h xfdl interrupt status 036h 0b6h 136h 1b6h xfdl transmit data 037h 0b7h 137h 1b7h xfdl reserved 038h 0b8h 138h 1b8h rfdl configuration 039h 0b9h 139h 1b9h rfdl interrupt control/status 03ah 0bah 13ah 1bah rfdl status 03bh 0bbh 13bh 1bbh rfdl receive data 03ch 0bch 13ch 1bch interrupt id (reg 03ch only)/clock monitor 03dh 0bdh 13dh 1bdh backplane parity configuration and status 03eh 0beh 13eh 1beh reserved 03fh 0bfh 13fh 1bfh reserved 040h 0c0h 140h 1c0h sigx configuration 041h 0c1h 141h 1c1h sigx p access status 042h 0c2h 142h 1c2h sigx timeslot indirect address/control 043h 0c3h 143h 1c3h sigx timeslot indirect data buffer
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 51 address register #1 # 2 # 3 # 4 044h 0c4h 144h 1c4h tran configuration 045h 0c5h 145h 1c5h tran transmit alarm/diagnostic control 046h 0c6h 146h 1c6h tran international/national control 047h 0c7h 147h 1c7h tran extra bits control 048h 0c8h 148h 1c8h pmon control/status 049h 0c9h 149h 1c9h pmon fer count 04ah 0cah 14ah 1cah pmon febe count (lsb) 04bh 0cbh 14bh 1cbh pmon febe count (msb) 04ch 0cch 14ch 1cch pmon crc count (lsb) 04dh 0cdh 14dh 1cdh pmon crc count (msb) 04eh 0ceh 14eh 1ceh pmon lcv count (lsb) 04fh 0cfh 14fh 1cfh pmon lcv count (msb) 050h- 07fh 0d0h- 0ffh 150h- 17fh 1d0h- 1ffh reserved 200h-3ffh reserved for test
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 52 10 normal mode register description normal mode registers are used to configure and monitor the operation of the equad. normal mode registers (as opposed to test mode registers) are selected when a[9] is low. notes on normal mode register bits: 1. although the register bit descriptions for the four framers have been combined, each framer is completely independent of the others. 2. writing values into unused register bits has no effect. reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read. 3. all configuration bits that can be written into can also be read back. this allows the processor controlling the equad to determine the programming state of the chip. 4. writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. 5. writing into read-only normal mode register bit locations does not affect equad operation unless otherwise noted.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 53 register 000h, 080h, 100h, 180h: receive options bit type function default bit 7 r/w worderr 0 bit 6 r/w cntnfas 0 bit 5 r/w elstbyp 0 bit 4 r/w trslip 0 bit 3 unused x bit 2 r/w srsmfp 0 bit 1 r/w srcmfp 0 bit 0 r/w trken 0 this register allows software to configure the receive functions. worderr: the worderr bit determines how frame alignment signal (fas) errors are reported. when worderr is logic 1, one or more errors in the seven bit fas word results in a single framing error count. when worderr is logic 0, each error in a fas word results in a single framing error count. cntnfas: when the cntnfas bit is a logic 1, a zero in bit 2 of time slot 0 of non-frame alignment signal (nfas) frames results in an increment of the framing error count. if worderr is also a logic 1, the word is defined as the eight bits comprising the fas pattern and bit 2 of time slot 0 of the next nfas frame. when the cntnfas bit is a logic 0, only errors in the fas affect the framing error count. elstbyp: the elstbyp bit allows the elastic store (elst) block to be bypassed, eliminating the one frame delay incurred through the elst. when set to logic 1, the received data and clock inputs to elst are internally routed directly to the elst outputs. trslip: the trslip bit allows the elst block to be used to measure, through slip indications, the frequency difference between the recovered receive line clock
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 54 and the transmit clock driving the tran block when the elst is bypassed. when trslip is set to logic 1, the transmit clock input to tran is internally substituted for the brclk input to the system side of the elst. when trslip is set to logic 0, the brclk input is routed to the system side of the elst. the trslip bit should only be set if elstbyp is set to logic 1. srsmfp, srcmfp: the srsmfp and srcmfp bits select the output signal seen on the output rfp[x]. rfp[x] can be used to show the frame alignment when fractional e1 extraction is being used (rfrace1 is set to logic 1 in the datalink options register and the ch[32:1] bits are set appropriately in the channel select registers). the following table summarizes the four configurations: srsmfp srcmfp result 0 0 receive frame pulse output: rfp[x] pulses high for 1 rclko[x] cycle during bit 1 of each 256-bit frame, indicating the frame alignment of the rdlsig[x] fractional e1 data stream. 0 1 receive crc multiframe output: rfp[x] pulses high for 1 rclko[x] cycle during bit 1 of frame 1 of every 16 frame crc multiframe, indicating the crc multiframe alignment of the rdlsig[x] fractional e1 data stream. (even when crc multiframing is disabled, the rfp[x] output continues to indicate the position of bit 1 of the fas frame every 16 th frame.) 1 0 receive signaling multiframe output: rfp[x] pulses high for 1 rclko[x] cycle during bit 1 of frame 1 of the 16 frame signaling multiframe, indicating the signaling multiframe alignment of the rdlsig[x] fractional e1 data stream. (even when signaling multiframing is disabled, the rfp[x] output continues to indicate the position of bit 1 of every 16 th frame.)
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 55 srsmfp srcmfp result 1 1 receive composite multiframe output: rfp[x] goes high on the falling rclko[x] edge marking the beginning of bit 1 of frame 1 of every 16 frame signaling multiframe, indicating the signaling multiframe alignment of the rdlsig[x] fractional e1 data stream, and returns low on the falling rclko[x] edge marking the end of bit 1 of frame 1 of every 16 frame crc multiframe, indicating the crc multiframe alignment of the rdlsig[x] fractional e1 data stream. this mode allows both multiframe alignments to be decoded externally from the single rfp[x] signal. note that if the signaling and crc multiframe alignments are coincident, rfp[x] will pulse high for 1 rclko[x] cycle every 16 frames. trken: the trken bit enables receive trunk conditioning upon an out-of-frame- condition. if trken is logic 1, the contents of the elst idle code register are inserted into all time slots (including ts0 and ts16) of brpcm if the framer is out-of-basic frame (i.e. the oof status bit is logic 1). the trken bit only has effect if the brx2rail and elstbyp bits are both logic 0. if trken is a logic 0, receive trunk conditioning can still be performed on a per-timeslot basis via the sigx per-timeslot trunk conditioning data registers upon reset of the equad, these bits are cleared to zero.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 56 register 001h, 081h, 101h, 181h: receive backplane options bit type function default bit 7 r/w rclkosel 0 bit 6 unused x bit 5 r/w rxdmagat 0 bit 4 r/w rohm 0 bit 3 r/w brx2rail 0 bit 2 r/w brxsmfp 0 bit 1 r/w brxcmfp 0 bit 0 r/w oosmfais 0 this register allows software to configure the receive backplane interface format. rclkosel: the rclkosel bit selects the source of the rclko[x] output and the internal elastic store output clock. if rclkosel is a logic zero, rclko[x] is the recovered clock derived from rdp[x] and rdn[x] or rclki[x] and the internal elastic store output clock is brclk. if rclkosel is a logic one, rclko[x] and the internal elastic store output clock originate from the smooth 2.048 mhz clock generated by the djat phase locked loop. if the recovered clock is selected as the pll reference, the configuration implements jitter attenuation in the receive direction. see the operations section for details on this application. trslip must be set to logic 0. rxdmagat: the rxdmagat bit selects the gating of the rdlint[x] output with the rdleom[x] output when the internal hdlc receiver is used with dma. when rxdmagat is set to logic 1, the rdlint[x] dma output is gated with the rdleom[x] output so that rdlint[x] is forced to logic 0 when rdleom[x] is logic 1. when rxdmagat is set to logic 0, the rdlint[x] and rdleom[x] outputs operate independently. brx2rail: the brx2rail bit selects whether the backplane receive data signal on the multifunction outputs brpcm/brdp[x] and brsig/brdn[x] are in either dual
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 57 rail or single rail format. when brx2rail is set to logic 1, the multifunction pins become the brdp[x] and brdn[x] dual rail outputs, which contain the received positive and negative line pulses timed to the 2.048mhz receive line rate, rclko[x]. when brx2rail is set to logic 0, the multifunction pins become the brpcm[x] and brsig[x] digital outputs. oosmfais: this bit controls the receive backplane signaling trunk conditioning in an out of signaling multiframe condition. if oosmfais is set to a logic 0, an oosmf indication from the frmr does not affect the brsig[x] outputs. when oosmfais is a logic 1, an oosmf indication from the frmr will cause the brsig[x] outputs to be set to all 1's. rohm, brxsmfp, brxcmfp: the rohm, brxsmfp and brxcmfp bits select the output signal seen on the backplane output brfpo[x]. the following table summarizes the configurations: rohm brxsmfp brxcmfp result 0 0 0 backplane receive frame pulse output: brfpo[x] pulses high for 1 brclk cycle (or 1 rclko[x] cycle if elst is by-passed) during bit 1 of each 256-bit frame, indicating the frame alignment of the brpcm[x] data stream. 0 0 1 backplane receive crc multiframe output: brfpo[x] pulses high for 1 brclk cycle (or 1 rclko[x] cycle if elst is by-passed or rclkosel is set to logic 1) during bit 1 of frame 1 of every 16 frame crc multiframe, indicating the crc multiframe alignment of the brpcm[x] data stream. (even when crc multiframing is disabled, the brfpo[x] output continues to indicate the position of bit 1 of the fas frame every 16 th frame).
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 58 rohm brxsmfp brxcmfp result 0 1 0 backplane receive signaling multiframe output: brfpo[x] pulses high for 1 brclk cycle (or 1 rclko[x] cycle if elst is by-passed or rclkosel is set to logic 1) during bit 1 of frame 1 of the 16 frame signaling multiframe, indicating the signaling multiframe alignment of the brpcm[x] data stream. (even when signaling multiframing is disabled, the brfpo[x] output continues to indicate the position of bit 1 of every 16 th frame.) 0 1 1 backplane receive composite multiframe output: brfpo[x] goes high on the falling brclk edge (or rclko[x] edge if elst is by- passed or rclkosel is set to logic 1) marking the beginning of bit 1 of frame 1 of every 16 frame signaling multiframe, indicating the signaling multiframe alignment of the brpcm[x] data stream, and returns low on the falling brclk edge (or rclko[x] edge if elst is by-passed or rclkosel is set to logic 1) marking the end of bit 1 of frame 1 of every 16 frame crc multiframe, indicating the crc multiframe alignment of the brpcm[x] data stream. this mode allows both multiframe alignments to be decoded externally from the single brfpo[x] signal. note that if the signaling and crc multiframe alignments are coincident, brfpo[x] will pulse high for 1 brclk cycle (or rclko[x] cycle if elst is by-passed or rclkosel is set to logic 1) every 16 frames. 1 x x backplane receive overhead output: brfpo[x] is high for timeslot 0 and timeslot 16 of each 256-bit frame, indicating the overhead of the brpcm[x] data stream.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 59 upon reset of the equad, these bits are cleared to zero.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 60 register 002h, 082h, 102h, 182h: datalink options bit type function default bit 7 r/w rxdmasig 0 bit 6 r/w rfrace1 0 bit 5 r/w txdmasig 0 bit 4 r/w tfrace1 0 bit 3 r/w rdlinte 0 bit 2 r/w rdleome 0 bit 1 r/w tdlinte 0 bit 0 r/w tdludre 0 this register allows software to configure the datalink options. rxdmasig: the rxdmasig bit selects the internal hdlc receiver (rfdl) data-received interrupt (int) and end-of-message (eom) signals to be output on the rdlint[x] and rdleom[x] pins. when rxdmasig is set to logic 1, the rdlint[x] and rdleom[x] output pins can be used by a dma controller to process the datalink. when rxdmasig is set to logic 0, the rfdl int and eom signals are no longer available to a dma controller; the signals on rdlint[x] and rdleom[x] become the extracted datalink data and clock, rdlsig[x] and rdlclk[x]. in this mode, the data stream available on the rdlsig[x] output corresponds to the extracted datalink from time slot 16 or the time slot 0 national use bits depending on the state of the rxsaxen bits of the receive ts0 data link enable register. the rfrace1 bit takes precedent over rxdmasig. rfrace1: the rfrace1 bit selects whether a fractional e1 is extracted and made available on the rdlsig[x] output, or whether the rdlint/rdlsig[x] and rdleom/rdlclk[x] pins operate as defined by the rxdmasig bit. when rfrace1 is set to logic 1, the contents of the channel select registers determine which channels are output on rdlsig[x] with an aligned burst clock output on rdlclk[x]. when rfrace1 is set to logic 0, the rdlint/rdlsig[x] and rdleom/rdlclk[x] pins contain the signals selected by the rxdmasig bit.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 61 txdmasig: the txdmasig bit selects the internal hdlc transmitter (xfdl) request for service interrupt (int) and data underrun (udr) signals to be output on the tdlint[x] and tdludr[x] pins. when txdmasig is set to logic 1, the tdlint[x] and tdludr[x] output pins can be used by a dma controller to service the datalink. when txdmasig is set to logic 0, the xfdl int and udr signals are no longer available to a dma controller; the signals on tdlint[x] and tdludr[x] become the serial datalink data input and clock, tdlsig[x] and tdlclk[x]. in this mode an external controller is responsible for formatting the data stream presented on the tdlsig[x] input to correspond to the datalink in time slot 16 or the time slot 0 national use bits. if the tran block configuration dlen bit is logic 1 and the tran block configuration sigen bit is a logic 0, the tdlsig data stream is inserted into time slot 16 and the tdlclk[x] pin is a 50% duty cycle 64 khz clock; otherwise, the tdlsig[x] data stream is inserted into the time slot 0 national use positions enabled by the txsaxen bits. the tfrace1 bit takes precedent over txdmasig in the default case tdlclk[x] is a bursted 4 khz clock and tdlsig[x] is inserted into the ts0 sa4 bit. tfrace1: the tfrace1 bit selects whether a fractional e1 is inserted into a subset of the channels of each frame via the tdlsig[x] input, or whether the tdlint/tdlsig[x] and tdludr/tdlclk[x] pins operate as defined by the txdmasig bit. when tfrace1 is set to logic 1, the channel data is expected on tdlsig[x], sampled on the rising edge of a burst clock provided on tdlclk[x]. the channels inserted are determined by the channel select registers; all others are inserted through btpcm[x]. when tfrace1 is set to logic 0, the tdlint/tdlsig[x] and tdludr/tdlclk[x] pins contain the signals selected by the txdmasig bit. rdlinte: the rdlinte bit enables the rfdl received-data interrupt to also generate an interrupt on the microprocessor interrupt, intb. this allows a single microprocessor to service the rfdl without needing to interface to the dma control signals. when rdlinte is set to logic 1, an event causing an interrupt in the rfdl (which is visible on the rdlint output pin when rxdmasig is logic 1) also causes an interrupt to be generated on the intb output. when rdlinte is set to logic 0, an interrupt event in the rfdl does not cause an interrupt on intb.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 62 rdleome: the rdleome bit enables the rfdl end-of-message interrupt to also generate an interrupt on the microprocessor interrupt, intb. this allows a single microprocessor to service the rfdl without needing to interface to the dma control signals. when rdleome is set to logic 1, an end-of-message event causing an eom interrupt in the rfdl (which is visible on the rdleom output pin when rxdmasig is logic 1) also causes an interrupt to be generated on the intb output. when rdleome is set to logic 0, an eom interrupt event in the rfdl does not cause an interrupt on intb. note: within the rfdl, an end-of-message event causes an interrupt on both the eom and int rfdl interrupt outputs. see the operation section for further details on using the rfdl. tdlinte: the tdlinte bit enables the xfdl request for service interrupt to also generate an interrupt on the microprocessor interrupt, intb. this allows a single microprocessor to service the xfdl without needing to interface to the dma control signals. when tdlinte is set to logic 1, an request for service interrupt event in the xfdl (which is visible on the tdlint output pin when txdmasig is logic 1) also causes and interrupt to be generated on the intb output. when tdlinte is set to logic 0, an interrupt event in the xfdl does not cause an interrupt on intb. tdludre: the tdludre bit enables the xfdl transmit data underrun interrupt to also generate an interrupt on the microprocessor interrupt, intb. this allows a single microprocessor to service the xfdl without needing to interface to the dma control signals. when tdludre is set to logic 1, an underrun event causing an interrupt in the xfdl (which is visible on the tdludr output pin when txdmasig is logic 1) also causes and interrupt to be generated on the intb output. when tdludre is set to logic 0, an underrun event in the xfdl does not cause an interrupt on intb. upon reset of the equad, these bits are cleared to zero.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 63 register 003h, 083h, 103h, 183h: receive interface configuration bit type function default bit 7 unused x bit 6 unused x bit 5 r/w bpv 0 bit 4 r/w rdninv 0 bit 3 r/w rdpinv 0 bit 2 r/w runi 0 bit 1 r/w rfall 0 bit 0 unused x this register enables the receive interface to handle the various input waveform formats. bpv: the bpv bit enables only bipolar violations to indicate line code violations and be accumulated in the pmon lcv count registers. when bpv is set to logic 1, bpvs (which are not part of a valid hdb3 signature if hdb3 line coding is used) generate an lcv indication and increment the pmon lcv counter. when bpv is set to logic 0, both bpvs (which are not part of a valid hdb3 signature if hdb3 line coding is used) and excessive zeros generate an lcv indication and increment the pmon lcv counter. excessive zeros is a sequence of zeros greater than 3 bits long for both ami and hdb3 encoded signals. rdpinv,rdninv: the rdpinv and rdninv bits enable the receive interface to logically invert the signals received on multifunction pins rdp/rdd[x] and rdn/rlcv[x], respectively. when rdpinv is set to logic 1, the interface inverts the signal on the rdp/rdd[x] input. when rdpinv is set to logic 0, the interface passes the rdp/rdd[x] signal unaltered. when rdninv is set to logic 1, the interface inverts the signal on the rdn/rlcv[x] input. when rdninv is set to logic 0, the interface passes the rdn/rlcv[x] signal unaltered.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 64 runi: the runi bit enables the interface to receive unipolar digital data and line code violation indications on the multifunction pins rdp/rdd[x] and rdn/rlcv[x]. when runi is set to logic 1, the rdp/rdd[x] and rdn/rlcv[x] multifunction pins become the data and line code violation inputs, rdd[x] and rlcv[x], sampled on the selected rclki[x] edge. when runi is set to logic 0, the rdp/rdd[x] and rdn/rlcv[x] multifunction pins become the positive and negative pulse inputs, rdp[x] and rdn[x], sampled on the selected rclki[x] edge. rfall: the rfall bit enables the receive interface to sample the multifunction pins on the falling rclki[x] edge. when rfall is set to logic 1, the interface is enabled to sample either the rdd[x] and rlcv[x] inputs, or the rdp[x] and rdn[x] inputs, on the falling rclki[x] edge. when rfall is set to logic 0, the interface is enabled to sample the inputs on the rising rclki[x] edge.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 65 register 004h, 084h, 104h, 184h: transmit interface configuration bit type function default bit 7 r/w fifobyp 0 bit 6 r/w taisen 0 bit 5 r/w tdninv 0 bit 4 r/w tdpinv 0 bit 3 r/w tuni 0 bit 2 r/w fifofull 0 bit 1 r/w trise 0 bit 0 r/w trz 0 this register enables the transmit interface to generate the required digital output waveform format. fifobyp: the fifobyp bit enables the transmit bipolar input signals to djat to be bypassed around the fifo to the bipolar outputs. when jitter attenuation is not being used the djat fifo can be bypassed to reduce the delay through the transmitter section by typically 24 bits. when fifobyp is set to logic 1, the bipolar inputs to djat are routed around the fifo and directly to the bipolar outputs. when fifobyp is set to logic 0, the bipolar transmit data passes through the djat fifo. note that when fifobyp is set to a logic 1, the oclksel1 bit in the transmit timing options register must also be set to logic 1. taisen: the taisen bit enables the interface to generate an unframed all-ones ais alarm on the tdp/tdd[x] and tdn[x] multifunction pins. when taisen is set to logic 1 and tuni is set to logic 0, the bipolar tdp[x] and tdn[x] outputs are forced to pulse alternately, creating an all-ones signal; when taisen and tuni are both set to logic 1, the unipolar tdd[x] output is forced to all-ones. when taisen is set to logic 0, the tdp/tdd[x] and tdn[x] multifunction outputs operate normally. the transition to transmitting ais on the tdp[x] and tdn[x] outputs is done in such a way as to not introduce any bipolar violations.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 66 tdpinv,tdninv: the tdpinv and tdninv bits enable the e1 transmit interface to logically invert the signals output on the tdp/tdd[x] and tdn/tflg [x] multifunction pins, respectively. when tdpinv is set to logic 1, the tdp/tdd[x] output is inverted. when tdpinv is set to logic 0, the tdp/tdd[x] output is not inverted. when tdninv is set to logic 1, the tdn/tflg[x] output is inverted. when tdninv is set to logic 0, the tdn/tflg[x] output is not inverted. tuni: the tuni bit enables the transmit interface to generate unipolar digital outputs on the tdp/tdd[x] and tdn/tflg[x] multifunction pins. when tuni is set to logic 1, the tdp/tdd[x] and tdn/tflg[x] multifunction pins become the unipolar outputs tdd[x] and tflg[x], updated on the selected tclko[x] edge. when tuni is set to logic 0, the tdp/tdd[x] and tdn/tflg[x] multifunction pins become the bipolar outputs tdp[x] and tdn[x], also updated on the selected tclko[x] edge. fifofull: the fifofull bit determines the indication given on the tflg[x] output pin. when fifofull is set to logic 1, the tflg[x] output indicates when the digital jitter attenuator's fifo is within 4 bit positions of becoming full. when fifofull is set to logic 0, the tflg[x] output indicates when the digital jitter attenuator's fifo is within 4 bit positions of becoming empty. trise: the trise bit configures the interface to update the multifunction outputs on the rising edge of tclko[x]. when trise is set to logic 1, the interface is enabled to update the tdp/tdd[x] and tdn/tflg[x] output pins on the rising tclko[x] edge. when trise is set to logic 0, the interface is enabled to update the outputs on the falling tclko[x] edge. trz: the trz bit configures the interface to transmit bipolar return-to-zero formatted waveforms. when trz is set to logic 1, the interface is enabled to generate the tdp[x] and tdn[x] output signals as rz waveforms with duration equal to half the tclko[x] period. when trz is set to logic 0, the interface is enabled to generate the tdp[x] and tdn[x] output signals as nrz waveforms with duration equal to the tclko[x] period, updated on the selected edge of tclko[x]. the trz bit can only be used when tuni and trise are set to logic 0.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 67 when the system is reset, the contents of the register are set to logic 0, enabling the transmit interface to output nrz formatted positive and negative pulse data on the tdp[x] and tdn[x] outputs, updated on the falling tclko[x] edge.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 68 register 005h, 085h, 105h, 185h: transmit backplane options bit type function default bit 7 unused x bit 6 unused x bit 5 r/w btfpref 0 bit 4 unused x bit 3 r/w btxclk 0 bit 2 unused x bit 1 r/w btx2rail 0 bit 0 r/w btxmfp 0 this register allows software to configure the transmit backplane interface format. btfpref: the btfpref bit selects the source of the input frame pulse. when btfpref is set to logic 1, btfp[1] is used as the input transmit frame pulse for the associated interface. if btfpref is set to logic 0, btfp[4:1] are used as the input transmit frame pulses for the associated interface. note that when btfpref is set to a logic 1, the corresponding btclk[x] must be phase aligned to btclk[1] to ensure proper sampling of btfp[1]. the btfpref bit in register 005h has no effect if menb is a logic 0. in this case, mtfp is used to generate internal frame pulses for each quadrant. btxclk: the btxclk bit selects the source of the tran transmit clock input signal. when btxclk is set to logic 1, the tran transmit clock is driven with the 2.048mhz recovered pcm output clock (rclko[x]) from the receiver section. when btxclk is set to logic 0, the tran transmit clock is driven with the 2.048mhz backplane transmit clock (btclk[x]). btx2rail: the btx2rail bit selects whether the backplane transmit data signal presented to the transmitter on the multifunction inputs btpcm/btdp[x] and btsig/btdn[x] are in either dual-rail or single-rail format. when btx2rail is set to logic 1, the multifunction pins become the btdp[x] and btdn[x]
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 69 dual-rail inputs, which bypass the tran and input directly into the jitter attenuator. it is expected that the framing bits be already inserted into the dual-rail streams before they are input on btdp[x] and btdn[x]. when btx2rail is set to logic 0, the multifunction pins become the btpcm[x] and btsig[x] digital inputs. btxmfp: the btxmfp bit selects the type of backplane frame alignment signal presented to the transmitter btfp[x] input. when btxmfp is set to logic 1, btfp[x] must be brought high to mark bit 1 of frame 1 of every 16 frame signaling multiframe and brought low following bit 1 of frame 1 of every 16 frame crc multiframe. this mode allows both multiframe alignments to be independently controlled using the single btfp[x] signal. note that if the signaling and crc multiframe alignments are coincident, btfp[x] must pulse high for 1 btclk[x] cycle at a multiple of 16 frames. when btxmfp is set to logic 0, a rising edge on the btfp[x] indicates the first bit in each frame. when the multiplexed transmit backplane is selected (menb is low), the btxmfp bit must be set to the same value in all four quadrants of the equad. the mtfp pin is used in a similar way as btfp[x] but is only sampled on the clock cycles corresponding to the first multiplexed pcm stream (destined for transmitter number one). mtfp must be brought high to mark bit 1 of frame 1 of the first multiplexed pcm stream (destined for transmitter number one) of every 16 frame signaling multiframe and brought low following bit 1 of frame 1 of the first multiplexed pcm stream of every 16 frame crc multiframe. all four interfaces will have the same frame alignment. upon reset of the equad, these bits are cleared to zero.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 70 register 006h, 086h, 106h, 186h: transmit framing options bit type function default bit 7 r/w pathcrc 0 bit 6 unused x bit 5 unused x bit 4 r/w txsa4en 1 bit 3 r/w txsa5en 0 bit 2 r/w txsa6en 0 bit 1 r/w txsa7en 0 bit 0 r/w txsa8en 0 pathcrc: the pathcrc bit allows upstream block errors to be preserved in the transmit crc bits. if pathcrc is a logic 1, the crc-4 bits are modified to reflect any bit values in btpcm[x] which have changed prior to transmission. when pathcrc is set to logic 0, the tran block is allowed to generate a new crc-4 value which overwrites the incoming crc-4 word. for the pathcrc bit to be effective, the btxmfp bit of the transmit backplane options register must be a logic 1; otherwise, the identification of the incoming crc-4 bits would be impossible. the pathcrc bit only takes effect if the gencrc bit of the tran configuration register (44h) is a logic 1 and either the indis or fdis bit in the same register are set to logic1. txsa4en, txsa5en, txsa6en, txsa7en and txsa8en: the txsaxen bits control the insertion of a data link into the time slot 0 national use bits (sa4 through sa8). these bits only have effect if the tran block configuration dlen bit is logic 0 or if the tran block configuration sigen bit is logic 1. the txsaxen bits take priority over the indis and fdis bits of the tran block configuration register. the data link bits are still inserted if either indis or fdis is logic 1. if the txdmasig bit is a logic 1, the data link bits are sourced by the internal hdlc transmitter; otherwise, the bits are sourced from the tdlsig[x] pin. if the txsa4en bit is logic 1, the tdlsig[x] value is written into bit 4 of time slot 0 of non-frame alignment signal frames. if the txsa8en bit is logic 1, the tdlsig[x] value is written into bit 8 of time slot 0 of non-frame alignment
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 71 signal frames. the other enable bits operate in an analogous fashion. a clock pulse is generated on tdlclk[x] for each enable that is logic 1. any combination of enable bits is allowed, resulting in a data rate between 4 kbit/s and 20 kbit/s. clearing all enable bits disables ts0 insertion. any national use bits which are not included in the data link are sourced from either btpcm[x] or the tran block international/national control register. upon reset of the equad, all bits are logic 0 except txsa4en. by default, a 4 kbit/s data link is inserted into sa4 from the tdlsig[x] input.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 72 register 007h, 087h, 107h, 187h: transmit timing options bit type function default bit 7 r/w hsbpsel 0 bit 6 r/w xclksel 0 bit 5 r/w oclksel1 0 bit 4 r/w oclksel0 0 bit 3 r/w pllref1 0 bit 2 r/w pllref0 0 bit 1 r/w tclkisel 0 bit 0 r/w smclko 0 this register allows software to configure the options of the transmit timing section. hsbpsel: the hsbpsel bit selects the source of the high-speed clock used in the elst, sigx and tpsc blocks. this allows the equad to interface to higher rate backplanes (>2.048mhz) that are externally gapped; however, the instantaneous backplane clock frequency must not exceed 3.0mhz. when hsbpsel is set to logic 1, the xclk input signal is divided by 2 and used as the high-speed clock to these blocks. xclk must be driven with 49.152mhz. when hsbpsel is set to logic 0, the block high-speed clock is driven with the internal 16.384mhz clock source selected by the xclksel bit. xclksel: the xclksel bit selects the source of the high-speed clock used in the cdrc, frmr, and pmon blocks. when xclksel is set to logic 1, the xclk input signal is used as the high-speed clock to these blocks. xclk must be driven with 16.384mhz. when xclksel is set to logic 0, the block high-speed clock is driven with xclk divided by 3. xclk must be driven with 49.152mhz. oclksel1, oclksel0: the oclksel[1:0] bits select the source of the digital jitter attenuator fifo output clock signal. when oclksel1 is set to logic 1, the djat fifo output clock is driven with the input data clock driving the djat iclk input. in this
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 73 mode the jitter attenuation is disabled and the input clock must be jitter-free. when oclksel1 is set to logic 0, the djat fifo output clock is driven with either the tclki[x] input clock or an internal smooth 2.048mhz clock, as selected by the oclksel0 bit. when oclksel0 is set to logic 1, the djat fifo output clock is driven with the tclki[x] input clock. when oclksel0 is set to logic 0, the djat fifo output clock is driven with the internal smooth 2.048 mhz clock selected by the tclkisel and smclko bits. in the case where the fifobyp bit in the transmit interface configuration register is set to a logic 1, the oclksel1 but must be set to a logic 1. pllref1, pllref0: the pllref[1:0] bits select the source of the digital jitter attenuator phase locked loop reference signal as follows: pllref1 pllref0 source of pll reference 0 0 transmit clock used by tran ( either the 2.048mhz btclk[x] or the 2.048mhz rclko[x], as selected by the btxclk register bit) 0 1 btclk[x] input 1 0 rclko[x] output 1 1 tclki[x] input tclkisel,smclko: the tclkisel and smclko bits select the source of the internal smooth 2.048mhz and 16.384mhz output clock signals. when tclkisel and smclko are set to logic 0, the internal 2.048mhz clock signal is driven by the smooth 2.048mhz clock source generated by djat. when tclkisel is set to logic 0 and smclko is set to logic 1, the internal 2.048mhz clock signal is driven by the tclki[x] input signal divided by 8, and the internal 16.384mhz clock signal is driven by the tclki[x] input signal. when tclkisel and smclko are set to logic 1, the internal 2.048mhz clock signal is driven by the xclk input signal divided by 8, and the internal 16.384mhz clock signal is driven by the xclk input signal. the combination of tclkisel set to logic 1 and smclko set to logic 0 should not be used. the following table illustrates the required bit settings for these various clock sources to affect the transmitted data:
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 74 ta bl e 2 - input transmit data bit settings xclk freq effect on output transmit data backplane transmit data timed to 2.048 mhz btclk[x]. hsbpsel =0 xclksel =0 oclksel1 =0 oclksel0 =0 pllref1 =0 pllref0 =x tclkisel =0 smclko =0 pllref1 =1 pllref0 =0 pllref1 =1 pllref0 =1 49.152mhz jitter attenuated. tclko[x] is a smooth 2.048 mhz. tclko[x] referenced to btclk[x]. tclko[x] referenced to rclko[x]. tclko[x] referenced to tclki[x]. backplane transmit data timed to >2.048mhz backplane clock. btclk[x] is externally "gapped". hsbpsel =1 xclksel =0 oclksel1 =0 oclksel0 =0 pllref1 =0 pllref0 =x tclkisel =0 smclko =0 pllref1 =1 pllref0 =0 pllref1 =1 pllref0 =1 49.152mhz jitter attenuated. tclko[x] is a smooth 2.048mhz. tclko[x] referenced to externally "gapped" transmit clock. tclko[x] referenced to rclko. tclko[x] referenced to tclki. backplane transmit data timed to btclk[x]. hsbpsel =0 xclksel =0 oclksel1 =1 oclksel0 =x pllref1 =x pllref0 =x tclkisel =0 smclko =0 xclksel =1 tclkisel =1 smclko =1 djat sync =0 49.152mhz 16.384mhz no jitter attenuation. tclko[x] is equal to internal transmit clock, either btclk[x], gapped btclk[x], or rclko[x]. same as above.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 75 input transmit data bit settings xclk freq effect on output transmit data backplane transmit data timed to btclk[x]. hsbpsel =0 xclksel =0 oclksel1 =0 oclksel0 =1 pllref1 =x pllref0 =x tclkisel =0 smclko =0 xclksel =1 tclkisel =1 smclko =1 49.152mhz 16.384mhz no jitter attenuation. tclko[x] is equal to tclki[x] (useful for higher rate mux applications). same as above. backplane transmit data timed to btclk[x]. hsbpsel =0 xclksel =0 oclksel1 =0 oclksel0 =0 pllref1 =x pllref0 =x tclkisel =0 smclko =1 xclksel =1 49.152mhz 16.384mhz tclki[x] is a jitter-free 16.384mhz clock. tclko[x] is equal to tclki[x]8. 1 same as above. backplane transmit data timed to btclk[x]. hsbpsel =0 xclksel =1 oclksel1 =0 oclksel0 =0 pllref1 =x pllref0 =x tclkisel =1 smclko =1 jitter-free 16.384mhz xclk is a jitter-free 16.384mhz clock. tclko[x] is equal to xclk8. 1 1. the register bits sync, cent, and limit in the djat configuration register must be set to logic 0 in these configurations. upon reset of the equad, these bits are cleared to zero, selecting digital jitter attenuation with tclko[x] referenced to the backplane transmit clock, btclk[x]. figure 8 illustrates the various bit setting options, with the reset condition highlighted.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 76 figure 8 - transmit timing options 11 djat fifo btclk[x] btxclk fifo input data clock 0 1 oclksel1 djat pll 01 10 pllref[1:0] 00 rclko[x] tclki[x] 0 1 smclko 0 1 smooth 2.048mhz smooth 16.384 mhz 1 0 8 oclksel0 0 1 tclkisel xclk 0 1 xclksel 0 1 hsbpsel 2 (49.152mhz or 16.384mhz) "jitter-free" 2.048mhz "jitter-free" 16.384mhz "high-speed" clock for cdrc & frmr (=16.384mhz) "high-speed" clock for elst, sigx, tpsc & rpsc (?6x max backplane clockrate) fifo output data clock tclko[x] 0 1 3 24x reference clock for jitter attenuation this diagram illustrates clock configurations for when the rclkosel bit is set to logic 0. see the operations - receiver jitter attenuation section for djat clock configurations when rclkosel is set to logic 1. the djat requires a 49.152mhz clock; if a 16.384mhz clock is used for xclk, then the djat will not function and should be bypassed.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 77 register 008h, 088h, 108h, 188h: interrupt source bit type function default bit 7 r djat 0 bit 6 r parity 0 bit 5 r frmr/sa 0 bit 4 r pmon 0 bit 3 r elst 0 bit 2 r rfdl 0 bit 1 r xfdl 0 bit 0 r cdrc 0 this register allows software to determine the block which produced the interrupt on the intb output pin. the frmr/sa bit is a logic 1 if either the frmr or the saci bit (register 009h, receive ts0 data link enable register) is the source of the interrupt. reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 78 register 009h, 089h, 109h, 189h: receive ts0 data link enables bit type function default bit 7 unused x bit 6 r/w sace 0 bit 5 r saci 0 bit 4 r/w rxsa4en 1 bit 3 r/w rxsa5en 0 bit 2 r/w rxsa6en 0 bit 1 r/w rxsa7en 0 bit 0 r/w rxsa8en 0 sace: the sace bit enables the generation of an interrupt whenever there is a change in the national bits that are not extracted to form a data link. changes in the national bits are not debounced, i.e. the interrupt is generated immediately when the current value of the national bits differs from the previous value. the value of the national bits can be read in the frmr international/national bits register. saci: the saci bit is set to logic one whenever there is a change in the national bits that are not extracted to form a data link. the saci bit is cleared following a read of this register. rxsa4en, rxsa5en, rxsa6en, rxsa7en and rxsa8en: the rxsaxen bits control the extraction of a data link from the received time slot 0 national use bits (sa4 through sa8). if rxdmasig bit is set to logic one, the data link bits are terminated by the internal hdlc receiver. if rxdmasig is set to logic 0, the data link is presented on rdlsig[x]. if the rxsa4en is logic 1, the rdlsig[x] value is extracted from bit 4 of time slot 0 of non-frame alignment signal frames. if the rxsa8en is logic 1, the rdlsig[x] value is extracted from bit 8 of time slot 0 of non-frame alignment signal frames. the other enable bits operate in an analogous fashion. a clock pulse is generated on rdlclk[x] for each enable
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 79 that is logic 1. any combination enable bits is allowed resulting in a data rate between 4 kbit/s and 20 kbit/s. if all rxsaxen (where x is the values 4 to 8 inclusive) bits are set to logic 0, timeslot 16 is extracted and treated as a data link. if rxdmasig is set to logic 0, timeslot16 is made available on the rdlsig[x] output and rdlclk[x] is an associated 64 khz clock. if rxdmasig is logic 1, the data link is terminated by the hdlc receiver and the rdlint/rdlsig[x] and rdleom/rdlclk[x] pins operate as a data link interrupt (rdlint[x]) and a end-of-message (rdleom[x]) indication. note that the rfrace1 bit will force fractional e1 channel outputs on rdlint/rdlsig[x] and rdleom/rdlclk[x] if it is set to logic 1 as it has the highest priority over the control of these outputs. upon reset of the equad, all bits are logic 0 except rxsa4en. by default, a 4 kbit/s data link is extracted from sa4 and presented on the rdlsig output.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 80 register 00ah, 08ah, 10ah, 18ah: master diagnostics bit type function default bit 7 unused x bit 6 unused x bit 5 r/w paylb 0 bit 4 r/w linelb 0 bit 3 unused x bit 2 r/w ddlb 0 bit 1 unused x bit 0 r/w txdis 0 this register allows software to enable diagnostic modes. paylb: the paylb bit selects the payload loopback mode, where the received data output from the elst is internally connected to the transmit data input of the tran. the data read out of elst is timed to the transmitter clock, and the transmit frame alignment is used to synchronize the output frame alignment of elst. during payload loopback, the data output on brpcm[x] is forced to logic 1. when paylb is set to logic 1, the payload loopback mode is enabled. when paylb is set to logic 0, the loopback mode is disabled. linelb: the linelb bit selects the line loopback mode, where the recovered positive and negative pulse outputs from the cdrc block are internally connected to the digital inputs of the djat. when linelb is set to logic 1, the line loopback mode is enabled. when linelb is set to logic 0, the line loopback mode is disabled. note that when line loopback is enabled, the timing options register settings should be reviewed to ensure the options are such that data will pass error-free and "jitter"-free through djat (typically, the default setting, 00h, for register 7 will be appropriate for line loopback). ddlb: the ddlb bit selects the diagnostic digital loopback mode, where the transmit side outputs from djat are internally connected to the receive side inputs. when ddlb is set to logic 1, the diagnostic digital loopback mode is
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 81 enabled. when ddlb is set to logic 0, the diagnostic digital loopback mode is disabled. the diagnostic digital loopback mode will operate with cdrc clock recovery enabled or disabled and in unipolar or bipolar mode. txdis: the txdis bit provides a method of suppressing the output of the transmitter. when txdis is set to logic 1, the digital output of tran is disabled by forcing it to logic 0. when txdis is set to logic 0, the digital output of tran is not suppressed. zeroing of the transmitter takes place before hdb3 encoding. in order to generate an all-zero's output, txdis and ami encoding (in the e1 tran configuration register) should be set. upon reset of the equad, these register bits are cleared to zero.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 82 register 00bh, 20bh: equad master test bit type function default bit 7 w tst x bit 6 r/w a_tm[8] x bit 5 r/w a_tm[7] x bit 4 w pmctst x bit 3 w dbctrl 0 bit 2 r/w iotst 0 bit 1 w hizdata 0 bit 0 r/w hizio 0 this register is used to select equad test features. all bits, except for pmctst and a_tm[8:7] are reset to zero by a hardware reset of the equad; a software reset of the equad does not affect the state of the bits in this register. refer to the test features description section for more information. tst: the tst bit performs a function similar to the pmctst bit (see below), but does not select a_tm[8:7] internally. a_tm[8]: the state of the a_tm[8] bit internally replaces the input address line a[8] when pmctst is set. this allows for more efficient use of the pmc manufacturing test vectors. a_tm[7]: the state of the a_tm[7] bit internally replaces the input address line a[7] when pmctst is set. this allows for more efficient use of the pmc manufacturing test vectors. pmctst: the pmctst bit is used to configure the equad for pmc's manufacturing tests. when pmctst is set to logic 1, the equad microprocessor port becomes the test access port used to run the pmc manufacturing test vectors. the pmctst bit is logically "ored" with the iotst bit, and is cleared by setting csb to logic 1.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 83 dbctrl: the dbctrl bit is used to pass control of the data bus drivers to the csb pin. when the dbctrl bit is set to logic 1, the csb pin controls the output enable for the data bus. while the dbctrl bit is set, holding the csb pin high causes the equad to drive the data bus and holding the csb pin low tri-states the data bus. the dbctrl bit overrides the hizdata bit. the dbctrl bit only has effect if either the iotst or pmctst bit is set. the dbctrl bit is used to measure the drive capability of the data bus driver pads. iotst: the iotst bit is used to allow normal microprocessor access to the test registers and control the test mode in each block in the equad for board level testing. when iotst is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequently the device outputs (refer to the "test mode 0 details" in the "test features" section). hizio,hizdata: the hizio and hizdata bits control the tri-state modes of the equad . while the hizio bit is a logic 1, all output pins of the equad except the data bus are held in a high-impedance state. the microprocessor interface is still active. while the hizdata bit is a logic 1, the data bus is also held in a high- impedance state which inhibits microprocessor read cycles.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 84 register 00ch: equad revision/chip id/global pmon update bit type function default bit 7 r type[2] 0 bit 6 r type[1] 0 bit 5 r type[0] 1 bit 4 r id[4] 0 bit 3 r id[3] 0 bit 2 r id[2] 0 bit 1 r id[1] 0 bit 0 r id[0] 1 the version identification bits, id[4:0], are set to a fixed value representing the version number of the equad. the chip identification bits, type[2:0], is set to logic 1 representing the equad. writing any value to this register causes all performance monitor counters to be updated simultaneously.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 85 register 00dh, 08dh, 10dh, 18dh: framer reset bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r/w reset 0 reset: the reset bit implements a software reset to the corresponding quadrant of the equad. if the reset bit is a logic 1, the individual framer is held in reset. this bit is not self-clearing; therefore, a logic 0 must be written to bring the framer out of reset. holding the framer in a reset state effectively puts it into a low power, stand-by mode. a hardware reset clears the reset bit, thus deasserting the software reset.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 86 register 00eh, 08eh, 10eh, 18eh: phase status word (lsb) bit type function default bit 7 r psb[7] x bit 6 r psb[6] x bit 5 r psb[5] x bit 4 r psb[4] x bit 3 r psb[3] x bit 2 r psb[2] x bit 1 r psb[1] x bit 0 r psb[0] x this register contains the least significant byte, psb[7:0], of the 9-bit phase status word. the 9-bit phase status word indicates the relative phase difference between the received e1 line timing (available on rclko[x]) and system timing. by utilizing the value of the phase status word, the system timing can be locked to the receive line timing via an external software controlled phase-locked-loop. the least significant 8 bits contained in this register indicate a count value (0- 255) of the number of system backplane clock cycles between successive 125s frame pulses. the most significant 5 bits (psb[7:3]) represent a time slot number (0-31) and the least significant 3 bits (psb[2:0]) represent the bit number within the timeslot (0-7). the count value corresponds to the location within the system frame where the receive line-timed frame pulse occurred. if the received line clock frequency is higher on average than the system clock frequency, the phase status word value will be seen to decrease during successive register reads. if the received line clock frequency is lower on average than the system clock frequency, the phase status word value will be seen to increase during successive register reads. the 9th bit of the phase status word indicates the "frame count" and will toggle when two successive 8-bit counter values straddle a frame boundary. the psb[8] bit will toggle when the bit and timeslot count indicated by psb[7:0] exceeds timeslot 31, bit 7 or the count goes below timeslot 0, bit 0. this is determined by comparing the psb[7:6] bits of the current phase status word value to those of the previous word value; psb[8] is toggled only under the following conditions (all other bit value transitions leave psb[8] unchanged):
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 87 ta bl e 3 - previous psb[7:6] current psb[7:6] effect on psb[8] 00 11 toggle 11 00 toggle the contents of the phase status word registers (address 00eh and 00fh for framer number 1) are internally updated on each receive line data frame pulse; a write to either register address (00eh or 00fh for framer number 1) must be performed to freeze the contents before this register and the phase status word (msb) register can be read. the correct sequence for reading the contents of the phase status word of framer number 1 are: 1. write to register address 00eh or 00fh 2. read register address 00fh (read phase status word msb) 3. read register address 00eh (read phase status word lsb) this write-before-read is analogous to the latching of performance monitor counter values in pmon, and is required to ensure that the phase status word value remains valid during the p read. it is important to read the msb register before the lsb register because, once the phase status word (lsb) register has been read, the phase status word counter is unfrozen and the contents may change immediately.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 88 register 00fh, 08fh, 10fh, 18fh: phase status word (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r psb[8] x this register contains the most significant bit of the 9-bit phase status word. the psb[8] bit toggles when the bit and timeslot count (from the phase status word lsb register) exceeds time slot 31, bit 7 or goes below time slot 0, bit 0. the contents of the phase status word registers are internally updated on each receive line data frame pulse; a write to either phase status word register address must be performed to freeze the contents before this register and the phase status word (msb) register can be read. the correct sequence for reading the contents of the phase status word are: 1. write to either phase status word register 2. read phase status word msb 3. read phase status word lsb this write-before-read is analogous to the latching of performance monitor counter values in pmon, and is required to ensure that the phase status word value remains valid during the p read. it is important to read the msb register before the lsb register because, once the phase status word (lsb) register has been read, the phase status word counter is unfrozen and the contents may change immediately.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 89 register 010h, 090h, 110h, 190h: cdrc configuration bit type function default bit 7 r/w ami 0 bit 6 r/w los1 0 bit 5 r/w los0 0 bit 4 r/w dcr 0 bit 3 r/w reserved 0 bit 2 r/w algsel 0 bit 1 r/w o162 0 bit 0 unused x ami: the active high ami bit disables hdb3 decoding. with ami low, an hdb3 signature on the rp and rn inputs is substituted with four zeros on the drpcm output. the ami bit has no affect on the rpcm output. los1, los0 the loss of signal threshold is set by the state of the ami, los1 and los0 bits: ami los1 los0 threshold (pcm periods) 00 010 10 015 x0 131 x1 063 x 1 1 175 if the number of consecutive spaces exceeds the programmed threshold, loss of signal is declared.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 90 dcr: asserting the dcr bit disables clock recovery. with dcr high, the recovered clock (rclko[x]) is derived from rclki[x] instead of being recovered from the rdp[x] and rdn[x] inputs. reserved: the reserved bit must be cleared to logic 0 for correct operation. algsel: the algorithm select (algsel) bit determines the dpll phase adjustment algorithm. a logic 0 selects the original phase adjustment algorithm which has 0.41 uipp of high frequency jitter tolerance. when algsel is logic 1, the high frequency jitter tolerance is 0.50 uipp, but the low frequency tolerance is approximately 20% lower than the first algorithm. o162: if the ami bit is logic 0, the itu-t recommendation o.162 compatibility select bit (o162) allows selection between two line code definitions: 1. if o162 is a logic 0, a line code violation is indicated if the serial stream does not match the verbatim hdb3 definition given in recommendation g.703. a bipolar violation that is not part of an hdb3 signature or a bipolar violation in an hdb3 signature that is the same polarity as the last bipolar violation results in a line code violation indication. 2. if o162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same polarity as the last bipolar violation, as per itu-t recommendation o.162.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 91 register 011h, 091h, 111h, 191h: cdrc interrupt enable bit type function default bit 7 r/w lcve 0 bit 6 r/w lose 0 bit 5 r/w hdb3e 0 bit 4 r/w z4de 0 bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x the cdrc interrupt enable register allows the setting of specific events to cause an interrupt on the intb pin. the z4de, hdb3e, lose, and lcve bits of this register are interrupt enable bits used to select which of the indications (four consecutive zeros, hdb3 pattern, loss of signal, or line code violation) will generate an interrupt when their status changes. the occurrence of any of these events will generate an interrupt if there is a logic 1 in the corresponding bit position. when the equad is reset, z4de, hdb3e, lose, and lcve bits are set to logic 0, disabling any interrupt generation.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 92 register 012h, 092h, 112h, 192h: cdrc interrupt status bit type function default bit 7 r lcvi x bit 6 r losi x bit 5 r hdb3i x bit 4 r z4di x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r los x the lcvi, losi, hdb3i and z4di bits indicate which of the status events have occurred since the last read of this register. a logic 1 indicates the corresponding event was detected. these bits are cleared when the cdrc interrupt status register is read. lcvi: the lcvi bit is asserted if a line code violation is detected. if the ami bit of the cdrc configuration register is a logic 1, lcvi becomes a logic 1 if two consecutive marks are of the same polarity (i.e. on the same pin, rdp or rdn). if the ami and o162 bits of the cdrc configuration register are both logic 0, lcvi becomes a logic 1 if a bipolar violation (bpv) is of the same polarity as the previous bpv or if the bpv is not preceded by two spaces. if the ami bit is a logic 0 and the o162 bit is a logic 1, lcvi becomes a logic 1 if two consecutive bipolar violations are of the same polarity. losi: the losi bit is set high when the los status bit changes state. hdb3i: the hdb3i bit is set high if an hdb3 signature, which is a bipolar violation of the opposite polarity of the previous bipolar violation following two spaces, is detected in the received data stream. z4di: the z4di bit is set high if four consecutive spaces occur.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 93 los: the los bit is the loss of signal status. it is a logic 1 if the number of consecutive spaces exceeds the programmed threshold. the status is deasserted upon the reception of a single mark.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 94 register 013h, 093h, 113h, 193h: cdrc alternate loss of signal status bit type function default bit 7 r/w altlose 0 bit 6 r altlosi x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r altlos x the alternate loss of signal status provides a more stringent criteria for the deassertion of the alarm. altlose: if the altlose bit is a logic 1, an interrupt is generated when the altlos status bit changes state. altlosi: the losi bit is set high when the altlos status bit changes state. it is cleared when this register is read. altlos: the altlos bit is asserted when the number of consecutive zeros exceeds the threshold specified by the cdrc configuration register. the altlos bit is deasserted only after 255 bit periods during which no sequence of four zeros has been received.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 95 registers 014h, 094h, 114h and 194h: channel select (0 to 7) bit type function default bit 7 r/w ch[7] 0 bit 6 r/w ch[6] 0 bit 5 r/w ch[5] 0 bit 4 r/w ch[4] 0 bit 3 r/w ch[3] 0 bit 2 r/w ch[2] 0 bit 1 r/w ch[1] 0 bit 0 r/w ch[0] 0
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 96 registers 015h, 095h, 115h and 195h: channel select (8 to 15) bit type function default bit 7 r/w ch[15] 0 bit 6 r/w ch[14] 0 bit 5 r/w ch[13] 0 bit 4 r/w ch[12] 0 bit 3 r/w ch[11] 0 bit 2 r/w ch[10] 0 bit 1 r/w ch[9] 0 bit 0 r/w ch[8] 0
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 97 registers 016h, 096h, 116h and 196h: channel select (16 to 23) bit type function default bit 7 r/w ch[23] 0 bit 6 r/w ch[22] 0 bit 5 r/w ch[21] 0 bit 4 r/w ch[20] 0 bit 3 r/w ch[19] 0 bit 2 r/w ch[18] 0 bit 1 r/w ch[17] 0 bit 0 r/w ch[16] 0
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 98 registers 017h, 097h, 117h and 197h: channel select (24 to 31) bit type function default bit 7 r/w ch[31] 0 bit 6 r/w ch[30] 0 bit 5 r/w ch[29] 0 bit 4 r/w ch[28] 0 bit 3 r/w ch[27] 0 bit 2 r/w ch[26] 0 bit 1 r/w ch[25] 0 bit 0 r/w ch[24] 0 these registers determine which timeslots (ts) are presented on rdlsig[x] or inserted from tdlsig[x] when the rfrace1 or tfrace1 register bit is set to logic 1 respectively. if the rfrace1 register bit is a logic 1, each channel, overhead, or datalink timeslot for which the associated ch[x] bit is set (e.g. ch[16] corresponds to ts16) will be presented on the rdlsig[x] output. the rdlclk[x] output will generate a pulse for each extracted bit. if the tfrace1 register bit is a logic 1, the serial stream input on tdlsig[x] will replace the channel timeslot from btpcm[x] for which the associated ch[x] bit is set. the tdlclk[x] output will generate a pulse to clock in each defined bit. note that if ch[0] is set to logic 1, the tdlsig[x] input will overwrite any framing and overhead data that would otherwise be inserted into ts0 by the tran block. if ch[16] is set to logic 1, the tdlsig[x] input will be inserted into ts16 regardless of the settings of the sigen and dlen bits of the tran configuration register.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 99 register 018h, 098h, 118h, 198h: djat interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r ovri 0 bit 0 r undi 0 this register contains the indication of the djat fifo status. ovri: the ovri bit is asserted when an attempt is made to write data into the fifo when the fifo is already full. when ovri is a logic 1, an overrun event has occurred. undi: the undi bit is asserted when an attempt is made to read data from the fifo when the fifo is already empty. when undi is a logic 1, an underrun event has occurred.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 100 register 019h, 099h, 119h, 199h: djat reference clock divisor (n1) control bit type function default bit 7 r/w n1[7] 0 bit 6 r/w n1[6] 0 bit 5 r/w n1[5] 1 bit 4 r/w n1[4] 0 bit 3 r/w n1[3] 1 bit 2 r/w n1[2] 1 bit 1 r/w n1[1] 1 bit 0 r/w n1[0] 1 this register defines an 8-bit binary number, n1, which is one less than the magnitude of the divisor used to scale down the djat pll reference clock input. the ref divisor magnitude, (n1+1), is the ratio between the frequency of ref input and the frequency applied to the phase discriminator input. writing to this register will reset the pll and, if the sync bit in the djat configuration register is high, will also reset the fifo. upon reset of the equad, the default value of n1 is set to decimal 47 (2fh). consult the operations section for clarification of divisor selection criteria.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 101 register 01ah, 09ah, 11ah, 19ah: djat output clock divisor (n2) control bit type function default bit 7 r/w n2[7] 0 bit 6 r/w n2[6] 0 bit 5 r/w n2[5] 1 bit 4 r/w n2[4] 0 bit 3 r/w n2[3] 1 bit 2 r/w n2[2] 1 bit 1 r/w n2[1] 1 bit 0 r/w n2[0] 1 this register defines an 8-bit binary number, n2, which is one less than the magnitude of the divisor used to scale down the djat smooth output clock signal. the output clock divisor magnitude, (n2+1), is the ratio between the frequency of the smooth output clock and the frequency applied to the phase discriminator input. writing to this register will reset the pll and, if the sync bit is high, will also reset the fifo. upon reset of the equad, the default value of n2 is set to decimal 47 (2fh). consult the operations section for clarification of divisor selection criteria.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 102 register 01bh, 09bh, 11bh, 19bh: djat configuration bit type function default bit 7 unused x bit 6 unused x bit 5 r/w reserved 1 bit 4 r/w cent 0 bit 3 r/w unde 0 bit 2 r/w ovre 0 bit 1 r/w sync 1 bit 0 r/w limit 1 this register controls the operation of the djat fifo read and write pointers and controls the generation of interrupt by the fifo status. reserved: this bit should be written to a logic 1 for proper operation. cent: the cent bit allows the fifo to self-center its read pointer, maintaining the pointer at least 4 ui away from the fifo being empty or full. when cent is set to logic 1, the fifo is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. if an empty or full alarm occurs during this 384 ui period, then the period will be extended by the number of ui that the empty or full alarm persists. during the empty or full alarm conditions, data is lost. when cent is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during empty or full alarm conditions. the sync bit must be set to logic 0 in order to set the cent bit to logic 1. ovre,unde: the ovre and unde bits control the generation of an interrupt on the microprocessor intb pin when a fifo error event occurs. when ovre or unde is set to logic 1, an overrun event or underrun event, respectively, is allowed to generate an interrupt on the intb pin. when ovre or unde is set to logic 0, the fifo error events are disabled from generating an interrupt.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 103 sync: the sync bit enables the pll to synchronize the phase delay between the fifo input and output data to the phase delay between reference clock input and smooth output clock at the pll. for example, if the pll is operating so that the smooth output clock lags the reference clock by 24 ui, then the synchronization pulses that the pll sends to the fifo will force its output data to lag its input data by 24 ui. limit: the limit bit enables the pll to limit the jitter attenuation by enabling the fifo to increase or decrease the frequency of the smooth output clock whenever the fifo is within one unit interval (ui) of overflowing or underflowing. this limiting of jitter ensures that no data is lost during high phase shift conditions. when limit is set to logic 1, the pll jitter attenuation is limited. when limit is set to logic 0, the pll is allowed to operate normally. upon reset of the equad, the limit and sync bits are set to logic 1, and the ovre, unde, and cent bits are set to logic 0.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 104 register 01ch, 09ch, 11ch, 19ch: elst configuration bit type function default bit 7 r/w accel 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w ir 1 bit 0 r/w or 1 this register controls the format of the expected input frame to the elst block and the format of the generated output frame from the elst block. accel: the accel bit is used for production test purposes only. the accel bit must be programmed to logic 0 for normal operation. ir: the ir bit selects the input frame format. the ir bit must be set to logic 1 to properly handle the e1 frame format being input into the elst. setting ir to logic 0 is a reserved setting and should not be used. or: the or bit selects the output frame format. the or bit must be set to logic 1 to properly generate the e1 frame format output from the elst. setting or to logic 0 is a reserved setting and should not be used.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 105 register 01dh, 09dh, 11dh, 19dh: elst interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w slipe 0 bit 1 r slipd x bit 0 r slipi x slipe: the slipe bit position is an interrupt enable that when set, allows the int output to go high when a slip occurs. when the block is reset the slipe bit position is cleared and interrupt generation is disabled. slipd: the slipd bit indicates the direction of the last slip. if the interrupt status register is read and the slipd bit is a logic 1 then the last slip was due to the frame buffer becoming full. if the interrupt status register is read and the slipd bit is a logic 0 then the last slip was due to the frame buffer becoming empty. slipi: the slipi bit is set if a slip occurred since the last read of the interrupt status register. the slipi bit is cleared just after the interrupt status register read operation.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 106 register 01eh, 09eh, 11eh, 19eh: elst idle code bit type function default bit 7 r/w d7 1 bit 6 r/w d6 1 bit 5 r/w d5 1 bit 4 r/w d4 1 bit 3 r/w d3 1 bit 2 r/w d2 1 bit 1 r/w d1 1 bit 0 r/w d0 1 the contents of the idle code register replace the timeslot data in the brpcm serial data stream when the e1 framer is out of frame and the trken bit in the receive options register is a logic 1. since the transmission of all ones timeslot data is a common requirement, the idle code register is set to all ones on a reset condition. bit 7 is the first to be transmitted. the writing of the idle code pattern is asynchronous with respect to the output data clock. one timeslot of idle code data will be corrupted if the register is written to when the framer is out of frame.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 107 register 020h, 0a0h, 120h, 1a0h: frmr frame alignment options bit type function default bit 7 r/w crcen 0 bit 6 r/w casdis 0 bit 5 r/w afaa 0 bit 4 r/w chkseq 0 bit 3 r/w casa 0 bit 2 r/w refr 0 bit 1 r/w refcrce 0 bit 0 r/w refrdis 0 this register selects the various framing formats and framing algorithms supported by the frmr block. crcen: the crcen bit enables the frmr to frame to the crc multiframe. when the crcen bit is logic 1, the frmr searches for crc multiframe alignment and monitors for errors in the alignment. a logic 0 in the crcen bit position disables searching for multiframe and suppresses the crce, cmfer, and febe frmr status's, forcing them to logic 0 and forcing oocmf to a logic 1. casdis: the casdis bit enables the frmr to frame to the channel associated signaling multiframe when set to a logic 0. when cas is enabled, the frmr searches for signaling multiframe alignment and monitors for errors in the alignment. a logic 1 in the casdis bit position disables searching for multiframe and suppresses the oosmf and the smfer frmr outputs, forcing them to logic 0. afaa: the afaa bit enables an alternate framing algorithm. if afaa is a logic zero, frame alignment is declared after a correct fas, a logic 1 in bit 2 of time slot 0 of the next frame and finally another fas in the third frame are found. if one of the conditions fails, the next bit position is checked for valid framing. if afaa is a logic one, the framing is similar to the above, but adds a "hold-off" feature. if bit2 or the second 7-bit fas conditions fail, the same byte location
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 108 is checked again in the subsequent frames before checking the next bit position for frame alignment. chkseq: the chkseq bit enables the use of the check sequence to verify the correct frame alignment in the presence of random imitative frame alignment signals. a logic 1 in the chkseq bit position enables the use of the check sequence algorithm in addition to the basic frame find algorithms; a logic 0 disables the use of the check sequence algorithm. casa: the casa bit selects one of the two algorithms used to find channel associated signaling multiframe alignment. a logic 0 in the casa bit position selects the g.732-compatible algorithm; a logic 1 selects the alternate framing algorithm. refr: a transition from logic 0 to logic 1 in the refr bit position forces the re- synchronization to a new frame alignment. the bit must be cleared to logic 0, then set to logic 1 again to generate subsequent re-synchronizations. refcrce: the refcrce bit enables excessive crc errors (? 915 errors in one second) to force a re-synchronization to a new frame alignment. setting the refcrce bit position to logic 1 enables reframe due to excessive crc errors; setting the refcrce bit to logic 0 disables crc errors from causing a reframe. refrdis: the refrdis bit disables reframing under any error condition once frame alignment has been found; reframing can be initiated by software via the refr bit. a logic 1 in the refrdis bit position causes the frmr to remain "locked in frame" once initial frame alignment has been found. a logic 0 allows reframing to occur based on the various error criteria (fer, excessive crc errors, etc.). note that while the frmr remains locked in frame due to refrdis=1, a received ais will not be detected since the frmr must be out-of-frame to detect ais.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 109 register 021h, 0a1h, 121h, 1a1h: frmr maintenance mode options bit type function default bit 7 r/w fasc 0 bit 6 r/w bit2c 0 bit 5 r/w smfasc 0 bit 4 r/w t16c 0 bit 3 r/w radeb 0 bit 2 r/w rmadeb 0 bit 1 r cmfact x bit 0 r excrce x fasc: the fasc bit selects the criterion used to declare loss of frame alignment signal: a logic 0 in the fasc bit position enables declaration of loss of frame alignment when 3 consecutive frame alignment patterns have been received in error; a logic 1 in the fasc bit position enables declaration of loss of frame when 4 consecutive frame alignment pattern errors are detected. bit2c: the bit2c bit enables the additional criterion that loss of frame is declared when bit 2 in time slot 0 of nfas frames has been received in error on 3 consecutive occasions: a logic 1 in the bit2c position enables declaration of loss of frame alignment when bit 2 is received in error; a logic 0 in bit2c enables declaration of loss of frame alignment based on the setting of fasc, only. smfasc: the smfasc bit selects the criterion used to declare loss of signaling multiframe alignment signal: a logic 0 in the smfasc bit position enables declaration of loss of signaling multiframe alignment when 2 consecutive multiframe alignment patterns have been received in error; a logic 1 in the smfasc bit position enables declaration of loss of signaling multiframe when 2 consecutive multiframe alignment patterns have been received in error or when time slot 16 contains logic 0 in all bit positions for 1 or 2 multiframes based on the criterion selected by t16c.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 110 t16c: the t16c bit selects the criterion used to declare loss of signaling multiframe alignment signal when enabled by the smfasc: a logic 0 in the t16c bit position enables declaration of loss of signaling multiframe alignment when time slot 16 contains logic 0 in all bit positions for 1 multiframe; a logic 1 in the t16c bit position enables declaration of loss of signaling multiframe when time slot 16 contains logic 0 in all bit positions for 2 consecutive signaling multiframes. radeb: the radeb bit selects the amount of debouncing applied to the remote alarm indication before the rra is allowed to change state: a logic 0 in the radeb bit position enables the rra output to change to the logic value contained in the remote alarm bit position (bit 3 of nfas frames) when the received remote alarm bit value has been in the same state for 2 consecutive nfas frames; a logic 1 in the radeb bit position enables the rra output to change when the remote alarm bit has been in the same state for 3 consecutive nfas frames. rmadeb: the rmadeb bit selects the amount of debouncing applied to the remote signaling multiframe alarm indication before the rrma is allowed to change state: a logic 0 in the rmadeb bit position enables the rrma output to change to the logic value contained in the remote signaling multiframe alarm bit position (bit 6 of time slot 16 of frame 0 of the signaling multiframe) when the received remote signaling multiframe alarm bit value has been in the same state for 2 consecutive signaling multiframes; a logic 1 in the rmadeb bit position enables the rrma output to change when the remote signaling multiframe alarm bit has been in the same state for 3 consecutive signaling multiframes. cmfact: the cmfact bit is an active high status bit indicating that the crc multiframe find algorithm has been active for more than 8ms, thereby initiating a reframe if the crcen bit is set to logic 1. the cmfact bit is reset to logic 0 after the register is read. excrce: the excrce bit is an active high status bit indicating that excessive crc evaluation errors (i.e. ?915 error in one second) have occurred, thereby initiating a reframe if enabled by the refcrce bit of the frame alignment options register. the excrce bit is reset to logic 0 after the register is read.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 111 register 022h, 0a2h, 122h, 1a2h: frmr framing status interrupt enable bit type function default bit 7 unused x bit 6 r/w oofe 0 bit 5 r/w oosmfe 0 bit 4 r/w oocmfe 0 bit 3 r/w cofae 0 bit 2 r/w fere 0 bit 1 r/w smfere 0 bit 0 r/w cmfere 0 oofe, oosmfe and oocmfe: a logic one in bits oofe, oosmfe and oocmfe enables the generation of an interrupt on a change of state of oof, oosmf and oocmf bits respectively of the frmr framing status register. cofae: a logic one in the cofae bit enables the generation of an interrupt when the position of the frame alignment has changed. fere: a logic one in the fere bit enables the generation of an interrupt when an error has been detected in the frame alignment signal. smfere: a logic one in the smfere bit enables the generation of an interrupt when an error has been detected in the signaling multiframe alignment signal. cmfere: a logic one in the cmfere bit enables the generation of an interrupt when an error has been detected in the crc multiframe alignment signal.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 112 register 023h, 0a3h, 123h, 1a3h: frmr maintenance/alarm status interrupt enable bit type function default bit 7 r/w rrae 0 bit 6 r/w rrmae 0 bit 5 r/w aisde 0 bit 4 r/w t16aisde 0 bit 3 r/w rede 0 bit 2 r/w aise 0 bit 1 r/w febee 0 bit 0 r/w crcee 0 rrae, rrmae, aisde, t16aisde, rede and aise: a logic one in bits rrae, rrmae, aisde, t16aisde, rede or aise enables the generation of an interrupt on a change of state of the rra, rrma, aisd, t16aisd, red and ais bits respectively of the frmr maintenance/alarm status register. febee: when the febee bit is a logic one, an interrupt is generated when a logic zero is received in the si bits of frames 13 or 15. crcee: when the crcee bit is a logic one, an interrupt is generated when calculated crc differs from the received crc remainder.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 113 register 024h, 0a4h, 124h, 1a4h: frmr framing status interrupt indication bit type function default bit 7 unused x bit 6 r oofi x bit 5 r oosmfi x bit 4 r oocmfi x bit 3 r cofai x bit 2 r feri x bit 1 r smferi x bit 0 r cmferi x a logic 1 in any bit position of this register indicates which framing status generated an interrupt by changing state. oofi, oosmfi, oocmfi, and cofai: oofi, oosmfi, oocmfi, and cofai indicate when the corresponding status has changed state from logic 0 to logic 1 or vice-versa. feri, smferi, cmferi: feri, smferi, cmferi indicate when a framing error, signaling multiframe error or crc multiframe error event has been detected; these bits will be set if one or more errors have occurred since the last register read. the interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the state of the framer. the contents of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was generated by any of the framing status outputs.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 114 register 025h, 0a5h, 125h, 1a5h: frmr maintenance/alarm status interrupt indication bit type function default bit 7 r rrai x bit 6 r rrmai x bit 5 r aisdi x bit 4 r t16aisdi x bit 3 r redi x bit 2 r aisi x bit 1 r febei x bit 0 r crcei x a logic 1 in any bit position of this register indicates which maintenance or alarm status generated an interrupt by changing state. rrai, rrmai, aisdi, t16aisdi, redi, and aisi: rrai, rrmai, aisdi, t16aisdi, redi, and aisi indicate when the corresponding frmr maintenance/alarm status register bit has changed state from logic 0 to logic 1 or vice-versa. febei: the febei bit becomes a logic one when a logic zero is received in the si bits of frames 13 or 15. crcei: the crcei bit becomes a logic one when a calculated crc differs from the received crc remainder. the bits in this register are set by a single error event. the interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the state of the framer. the contents of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was generated by one of the maintenance/alarm status events.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 115 register 026h, 0a6h, 126h, 1a6h: frmr framing status bit type function default bit 7 unused x bit 6 r oof x bit 5 r oosmf x bit 4 r oocmf x bit 3 unused x bit 2 unused x bit 1 r/w 8msdis 0 bit 0 r/w mfasdis 0 reading this register returns the current state value of the oof, oosmf and oocmf frmr framing status. oof: the oof bit is a logic one when basic frame alignment has been lost. the oof bit goes to a logic zero once frame alignment has been regained. oosmf: the oosmf bit is a logic one when the signaling multiframe alignment has been lost. the oosmf bit becomes a logic zero once signaling multiframe has been regained. oocmf: the oocmf bit is a logic one when the crc multiframe alignment has been lost. the oocmf bit becomes a logic zero once crc multiframe has been regained. 8msdis: the 8msdis bit controls the ability of the 8 ms timer to initiate a reframe when crc multi-frame alignment cannot be found. when 8msdis is set to logic 0, the 8 ms timer will initiate a reframe when the crc multi-frame find algorithm has been active for more than 8 ms. when 8msdis is set to logic 1, the 8 ms timer will not initiate a reframe when the crc multi-frame find algorithm has been active for more than 8 ms.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 116 this bit is intended to be used for compatibility with itu-t g.706 section 4.2, note 2. mfasdis: the mfasdis bit controls the ability of the mfas errors to cause a loss of crc multiframe. when mfasdis is a logic 0, 4 consecutive mfass received in error will cause a loss of crc multiframe, indicated by oocmf = 1 and oof = 1. when mfasdis is a logic 1, crc multiframe alignment, once found, will not be lost unless there is a loss of basic frame alignment or excessive crc errors (> 915 per second) occur. this bit should be set to logic 1 for compliance to itu-t g.706.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 117 register 027h, 0a7h, 127h, 1a7h: frmr maintenance/alarm status bit type function default bit 7 r rra x bit 6 r rrma x bit 5 r aisd x bit 4 r t16aisd x bit 3 r red x bit 2 r ais x bit 1 unused x bit 0 unused x reading this register returns the current state value of the rra, rrma, aisd, t16aisd, red, and ais maintenance/alarm statuses. rra: the rra bit is a logic one when the "a" bit (bit 3 in time slot 0 of the non- frame alignment signal frame) has been a logic one for 2 or 3 consecutive non-frame alignment signal frames, as determined by the radeb bit. the rra output is updated every two frames. rrma: the rrma bit is a logic one when the "y" bit (bit 6 in time slot 16 in frame 0 of the signaling multiframes) has been a logic one for 2 or 3 consecutive signaling multiframes, as determined by the rmadeb bit. the rrma bit is updated every 16 frames. aisd: the aisd bit is a logic one after an unframed pattern of all ones with less than 3 zeros in two consecutive frame times (512 bits) has been detected. the aisd bit is updated every 512 bit times. ts16aisd: the ts16aisd is a logic one after an all-ones byte has been detected in time slot 16 for 2 consecutive frames while out of signaling multiframe alignment.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 118 red: the red bit is a logic one if an out of frame condition has persisted for 100 ms. the red bit returns to a logic zero when a out of frame condition has been absent for 100 ms. ais: the ais bit is a logic one when an out of frame all-ones condition has persisted for 100 ms. the ais bit returns to a logic zero when the ais condition has been absent for 100 ms.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 119 register 028h, 0a8h, 128h, 1a8h: frmr international/national bits bit type function default bit 7 r si1 x bit 6 r si0 x bit 5 r rawra x bit 4 r sn0 x bit 3 r sn1 x bit 2 r sn2 x bit 1 r sn3 x bit 0 r sn4 x reading this register returns the current bit value of the international and national bits collected over 2 consecutive frames. the si1 bit position corresponds to the value contained in the international bit position in the fas frame; the si0, rawra, and sn[4:0] bit positions correspond to the values contained in the international, remote alarm indication, and national bit positions in the nfas frame. this register is updated after time slot 0 of every nfas frame and the contents are valid for 2 frames (250s). the contents of this register are latched during the read, however the individual bits should not be considered to constitute a byte value (i.e. the 5 national bits should not be considered as indicating 1 of 32 possible values since it is possible that the individual bits are not all from the same time instant due to the asynchronous nature of the microprocessor reads). if the bits are to be interpreted as binary values, care should be taken to ensure a coherent set of bit values by reading the register at least twice. the si0, rawra and sn0-sn4 bits map to the tso nfas as follows: bit position 12 3 4 5 6 7 8 si0 1 rawra sn0 sn1 sn2 sn3 sn4
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 120 register 029h, 0a9h, 129h, 1a9h: frmr extra bits bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r x3 x bit 2 r rawrma x bit 1 r x1 x bit 0 r x0 x reading this register returns the current bit value of the extra bits and the remote signaling multiframe alarm collected from time slot 16 of frame 0 of signaling multiframes. the x3, rawrma, x1, x0 bit positions corresponds to the value contained in bit positions 5, 6, 7, and 8 in time slot 16 of frame 0 of the signaling multiframe. this register is updated once per signaling multiframe (the contents remain valid for 2ms). if the x3, x1, x0 bits are to be interpreted as binary values, care should be taken to ensure a coherent set of bit values by reading the register at least twice.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 121 register 02ah, 0aah, 12ah, 1aah: frmr crc error counter - lsb bit type function default bit 7 r crce7 x bit 6 r crce6 x bit 5 r crce5 x bit 4 r crce4 x bit 3 r crce3 x bit 2 r crce2 x bit 1 r crce1 x bit 0 r crce0 x this register contains the least significant byte of the 10-bit crc error counter value, updated every second.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 122 register 02bh, 0abh, 12bh, 1abh: frmr crc error counter - msb bit type function default bit 7 r ovr 0 bit 6 r newdata 0 bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r crce9 x bit 0 r crce8 x this register contains the most significant two bits of the 10-bit crc error counter value, updated every second. newdata: the newdata flag bit indicates that the counter register contents have been updated with a new count value accumulated over the last 1 second interval. it is set to logic 1 when the crc error counter data is transferred into the counter registers, and is reset to logic 0 when this register is read. this bit can be polled to determine the 1 second timing boundary used by the frmr. ovr: the ovr flag bit indicates that the counter register contents have not been read within the last 1 second interval, and therefore have been over-written. it is set to logic 1 if crc error counter data is transferred into the counter registers before the previous data has been read out, and is reset to logic 0 when this register is read. this crc error count is distinct from that of pmon because it is guaranteed to be an accurate count of the number of crc error in one second; whereas, pmon relies on externally initiated transfers which may not be one second apart.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 123 register 02ch, 0ach, 12ch, 1ach: ts16 ais alarm status bit type function default bit 7 unused x bit 6 r/w ts16aise 0 bit 5 r ts16aisi x bit 4 r t16ais x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x reading this register returns the current value of the time slot 16 ais status. the ts16 ais alarm algorithm accumulates the occurrences of ts16aisd (ts16 ais detection) events. ts16aisd is defined as two consecutive all ones time slot 16 bytes while out of signaling multiframe. each interval with a valid ts16 ais presence indication increments an interval counter which declares ts16 ais alarm when 22 valid intervals have been accumulated. an interval with no valid ts16 ais presence indication decrements the interval counter; the ts16 ais alarm declaration is removed when the counter reaches 0. this algorithm provides a 99.1% probability of declaring an ts16 ais alarm within 3.1 ms after loss of signaling multiframe detection in the presence of a 10 -3 mean bit error rate. ts16aise: if the ts16aise bit is a logic 1, an interrupt is generated when the ts16ais status bit changes state. ts16aisi: the ts16aisi bit is set high when the ts16ais status bit changes state. it is cleared when this register is read. ts16ais: the ts16ais bit is a logic one when an all ones condition has persisted in time slot 16 for 3 ms. the bit returns to a logic zero when the time slot 16 ais condition has been absent for 3 ms.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 124 register 030h, 0b0h, 130h, 1b0h: tpsc block configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w ind 0 bit 0 r/w pcce 0 this register allows selection of the microprocessor read access type and output enable control for the transmit per-channel serial controller. ind: the ind bit controls the microprocessor access type: either indirect or direct. the ind bit must be set to logic 1 for proper operation. when the equad is reset, the ind bit is set low, disabling the indirect access mode. pcce: the pcce bit enables the per-timeslot functions. when the pcce bit is set to a logic 1, each timeslot's data control byte and idle code byte are passed on to the tran block. when the pcce bit is set to logic 0, the per- timeslot functions are disabled.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 125 register 031h, 0b1h, 131h, 1b1h: tpsc block p access status bit type function default bit 7 r busy 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x busy: the busy bit in the status register is high while a p access request is in progress. the busy bit goes low timed to an internal high-speed clock rising edge after the access has been completed. during normal operation, the status register should be polled until the busy bit goes low before another p access request is initiated. a p access request is typically completed within 480 ns.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 126 register 032h, 0b2h, 132h, 1b2h: tpsc block timeslot indirect address/control bit type function default bit 7 r/w r/wb 0 bit 6 r/w a6 0 bit 5 r/w a5 0 bit 4 r/w a4 0 bit 3 r/w a3 0 bit 2 r/w a2 0 bit 1 r/w a1 0 bit 0 r/w a0 0 this register allows the p to access the internal tpsc registers addressed by the a[6:0] bits and perform the operation specified by the r/wb bit. writing to this register with a valid address and r/wb bit initiates an internal p access request cycle. the r/wb bit selects the operation to be performed on the addressed register: when r/wb is set to a logic 1, a read from the internal tpsc register is requested; when r/wb is set to a logic 0, an write to the internal tpsc register is requested.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 127 register 033h, 0b3h, 133h, 1b3h: tpsc block timeslot indirect data buffer bit type function default bit 7 r/w d7 0 bit 6 r/w d6 0 bit 5 r/w d5 0 bit 4 r/w d4 0 bit 3 r/w d3 0 bit 2 r/w d2 0 bit 1 r/w d1 0 bit 0 r/w d0 0 this register contains either the data to be written into the internal tpsc registers when a write request is initiated or the data read from the internal tpsc registers when a read request has completed. during normal operation, if data is to be written to the internal registers, the byte to be written must be written into this data register before the target register's address and r/wb=0 is written into the address/control register, initiating the access. if data is to be read from the internal registers, only the target register's address and r/wb=1 is written into the address/control register, initiating the request. after 480 ns, this register will contain the requested data byte. the internal tpsc registers control the per-timeslot functions on the transmit pcm data, provide the per-timeslot transmit idle code, and provide the per- timeslot transmit signaling control and the alternate signaling bits. the functions are allocated within the registers as follows:
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 128 20h data control byte for time slot 0 21h data control byte for time slot 1 22h data control byte for time slot 2 ?? ?? ?? 3eh data control byte for time slot 30 3fh data control byte for time slot 31 40h idle code byte for time slot 0 41h idle code byte for time slot 1 42h idle code byte for time slot 2 ?? ?? ?? 5eh idle code byte for time slot 30 5fh idle code byte for time slot 31 the bits within each control byte are allocated as follows:
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 129 tpsc internal registers 20-3fh: data control byte bit type function bit 7 r/w subs bit 6 r/w ds[0] bit 5 r/w ds[1] bit 4 r/w sigsrc bit 3 r/w a' bit 2 r/w b' bit 1 r/w c' bit 0 r/w d' subs, ds[1], and ds[0]: the subs, ds[1], and ds[0] bits select one of the following data manipulations to be performed on the timeslot: subs ds[0] ds[1] function 0 0 0 off - no change to pcm timeslot data 0 0 1 adi - data inversion on timeslot bits 1,3,5,7 0 1 0 adi - data inversion on timeslot bits 2,4,6,8 0 1 1 inv - data inversion on all timeslot bits 1 0 x data substitution on - idle code replaces pcm timeslot data 1 1 0 data substitution on - a-law digital milliwatt pattern * replaces tpcm timeslot data. 1 1 1 data substitution on - -law digital milliwatt pattern * replaces tpcm timeslot data.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 130 * the a-law digital milliwatt pattern used is that defined in recommendation g.711 for a-law: bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 00 1 1 0 1 0 0 00 1 0 0 0 0 1 00 1 0 0 0 0 1 00 1 1 0 1 0 0 10 1 1 0 1 0 0 10 1 0 0 0 0 1 10 1 0 0 0 0 1 10 1 1 0 1 0 0 * the -law digital milliwatt pattern used is that defined in recommendation g.711 for -law: bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 00 0 1 1 1 1 0 00 0 0 1 0 1 1 00 0 0 1 0 1 1 00 0 1 1 1 1 0 10 0 1 1 1 1 0 10 0 0 1 0 1 1 10 0 0 1 0 1 1 10 0 1 1 1 1 0 sigsrc: the sigsrc bit is valid only if channel associated signaling (cas) is selected in the tran configuration register; otherwise, it is ignored. when valid, the sigsrc bit selects the source of the timeslot signaling bits: if sigsrc is a logic 0, the signaling bits are taken from the incoming btsig stream in the format specified by the sigen and dlen bits in the tran configuration register; if sigsrc is a logic 1, the signaling bits are taken from the a',b',c', and d' bit .
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 131 tpsc internal registers 40-5fh: idle code byte bit type function bit 7 r/w idle7 bit 6 r/w idle6 bit 5 r/w idle5 bit 4 r/w idle4 bit 3 r/w idle3 bit 2 r/w idle2 bit 1 r/w idle1 bit 0 r/w idle0 the contents of the idle code byte register are substituted for the timeslot data on btpcm when the subs bit in the pcm control byte is set to a logic 1 and the ds[0] bit in the pcm control byte is set to a logic 0. the idle code is transmitted from msb (bit 7) to lsb (bit 0).
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 132 register 034h, 0b4h, 134h, 1b4h: xfdl block configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w eom 0 bit 3 r/w inte 0 bit 2 r/w abt 0 bit 1 r/w crc 0 bit 0 r/w en 0 eom: the eom bit indicates that the last byte of data written in the xfdl transmit data register is the end of the present data packet. if the crc bit is set then the 16-bit fcs word is appended to the last data byte transmitted and a continuous stream of flags is generated. the eom bit is automatically cleared before transmission of the next data packet begins. inte: the inte bit enables the generation of an interrupt via the tdlint[x] output. setting the inte bit to logic 1 enables the generation of an interrupt; setting inte to logic 0 disables the generation of an interrupt. if the tdlinte bit is also set to logic 1 in the datalink options register, the interrupt generated on the tdlint[x] output is also generated on the microprocessor intb pin. abt: the abort (abt) bit controls the sending of the 7 consecutive ones hdlc abort code. setting the abt bit to a logic 1 causes the 11111110 code to be transmitted after the last byte from the xfdl transmit data register is transmitted. aborts are continuously sent until this bit is reset to a logic 0. crc: the crc enable bit controls the generation of the itu-t-crc frame check sequence (fcs). setting the crc bit to logic 1 enables the itu-t-crc generator and the appends the 16 bit fcs to the end of each message. when the crc bit is set to logic 0, the fcs is not appended to the end of the
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 133 message. the crc type used is the itu-t-crc with generator polynomial = x 16 + x 12 +x 5 + 1. the high order bit of the fcs word is transmitted first. en: the enable bit (en) controls the overall operation of the xfdl block. when the en bit is set to a logic 1, the xdfl block is enabled and flag sequences are sent until data is written into the xfdl transmit data register. when the en bit is set to logic 0, the xfdl block is disabled.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 134 register 035h, 0b5h, 135h, 1b5h: xfdl interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r int 1 bit 0 r/w udr 0 int: the int bit indicates when the xfdl block is ready to accept a new data byte for transmission. the int bit is set to a logic 1 when the previous byte in the transmit data register has been loaded into the parallel to serial converter and a new byte can be written into the xfdl transmit data register. the int bit is set to a logic 0 while new data is in the transmit data register. the int bit is not disabled by the inte bit in the configuration register. udr: the udr bit indicates when the xfdl block has underrun the data in the xfdl transmit data register. the udr bit is set to a logic 1 if the parallel to serial conversion of the last byte in the xfdl transmit data register has completed before the new byte was written into the xfdl transmit data register. once an underrun has occurred, the xfdl transmits an abort, followed by a flag, and waits to transmit the next valid data byte. if the udr bit is still set after the transmission of the flag the xfdl will continuously transmit the all-ones idle pattern. the udr bit can only be cleared by writing a logic 0 to the udr bit position in this register.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 135 register 036h, 0b6h, 136h, 1b6h: xfdl transmit data bit type function default bit 7 r/w td7 x bit 6 r/w td6 x bit 5 r/w td5 x bit 4 r/w td4 x bit 3 r/w td3 x bit 2 r/w td2 x bit 1 r/w td1 x bit 0 r/w td0 x data written to this register is serialized and transmitted on the facility data link least significant bit first. the xfdl block signals when the next data byte is required by setting the tdlint[x] output high (if enabled) and by setting the int bit in the status register high. when int and/or tdlint[x] is set, the transmit data register must be written with the new data within 4 data bit periods to prevent the occurrence of an underrun.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 136 register 038h, 0b8h, 138h, 1b8h: rfdl configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w tr 0 bit 0 r/w en 0 tr: setting the terminate reception bit (tr) forces the rfdl block to immediately terminate the reception of the current lapd frame, empty the fifo, clear the interrupts, and begin searching for a new flag sequence. the rfdl handles the tr input in the same manner as if the en bit had been cleared and then set. the tr bit in the configuration register will reset itself after a rising and falling edge have occurred on the clk input to the rfdl block once the write to this register has completed and wrb goes inactive. if the configuration register is read after this time, the tr bit value returned will be zero. en: the enable bit (en) controls the overall operation of the rfdl block. when set, the rdfl block is enabled; when reset the rfdl block is disabled. when the block is disabled, the fifo and interrupts are all cleared, however, the programming of the rfdl interrupt control/status register is not affected. when the block is enabled, it will immediately begin looking for flags. the rfdl block handles the tr input in the same manner as clearing and setting the en bit, therefore, the rfdl state machine will begin searching for flags and an interrupt will be generated when the first flag is detected.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 137 register 039h, 0b9h, 139h, 1b9h: rfdl interrupt control/status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w intc1 0 bit 1 r/w intc0 0 bit 0 r int 0 intc1,intc0: the intc1 and intc0 bits control when an interrupt is asserted based on the number of received data bytes in the fifo as follows: intc1 intc0 description 0 0 disable interrupts (all sources) 0 1 enable interrupt when fifo receives data 1 0 enable interrupt when fifo has 2 bytes of data 1 1 enable interrupt when fifo has 3 bytes of data int: the int bit reflects the status of the external rdlint[x] interrupt unless the intc1 and intc0 bits are set to disable interrupts. in that case, the rdlint[x] output is forced to 0 and the int bit of this register will reflect the state of the internal interrupt latch. in addition to the fifo fill status, interrupts are also generated for eom (end of message), ovr (fifo overrun), detection of the abort sequence while not receiving all ones and on detection of the first flag while receiving all ones. the interrupt is reset by a rfdl receive data register read that empties the fifo, unless the cause of the interrupt was due to a fifo overrun. the interrupt due to
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 138 a fifo overrun is cleared by a rfdl status register read, by disabling the block, or by setting tr high. the contents of this register should only be changed when the rfdl block is disabled to prevent any erroneous interrupt generation.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 139 register 03ah, 0bah, 13ah, 1bah: rfdl status bit type function default bit 7 r fe 1 bit 6 r ovr 0 bit 5 r flg 0 bit 4 r eom 0 bit 3 r crc 0 bit 2 r nvb2 1 bit 1 r nvb1 1 bit 0 r nvb0 1 the flg and eom bits in this register contain values which correspond to the last byte read from the rfdl data register. fe: the fifo empty bit (fe) is high when the last fifo entry is read and goes low when the fifo is loaded with new data. ovr: the receiver overrun bit (ovr) is set when data is written over unread data in the fifo. this bit is not reset until after the rfdl status register is read. while ovr is high, the rfdl and fifo are held in the reset state, causing the flg and eom bits in the status register to be reset also. flg: the flag bit (flg) is set if the rfdl has detected the presence of the lapd flag sequence (01111110) in the data. flg is reset only when the lapd abort sequence (01111111) is detected in the data or when the rfdl is disabled. this bit is passed through the fifo with the data so that the status of this bit will correspond to the data just read from the rfdl data register. the reception of bit-oriented codes over the data link will also force an abort due to its eight ones pattern. eom: the end of message bit (eom) follows the rdleom[x] output. it is set when:
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 140 1) the last byte in the lapd frame (eom) is being read from the receive data register, 2) an abort sequence is detected while not in the receiving all-ones state and the byte, written to the fifo due to the detection of the abort sequence, is being read from the fifo, 3) the first flag has been detected and the dummy byte, written into the fifo when the rfdl changes from the receiving all-ones state to the receiving flags state, is being read from the fifo, 4) immediately on detection of fifo overrun. the eom bit is passed through the fifo with the data so that the status of this bit will correspond to the data just read from the rfdl data register. crc: the crc bit is set if a crc error was detected in the last received hdlc frame. the crc bit is only valid when eom is logic 1 and flg is a logic 1 and ovr is a logic 0. nvb[2:0]: the nvb[2:0] bit positions indicate the number of valid bits in the rfdl receive data register byte. it is possible that not all of the bits in the rfdl receive data register are valid when the last data byte is read since the data frame can be any number of bits in length and not necessarily an integral number of bytes. the rfdl receive data register is filled starting from the msb bit position (rd7) and the data bits are shifted to lower bit positions as more bits are received, with one to eight data bits being valid. the number of valid bits is equal to 1 plus the value of nvb[2:0]. an nvb[2:0] value of 000 binary indicates that only the fe bit in this register is valid. an nvb[2:0] value of 011 indicates that rd[7:4] contain valid data bits where rd4 is the data bit that was received first. nvb[2:0] is only valid when the eom bit is a logic 1 and the flg bit is a logic 1 and the ovr bit is a logic 0. on an interrupt generated from the detection of the first flag, reading the rfdl status register will return invalid nvb[2:0] and crc bits, even though the eom bit is logic 1 and the flg bit is logic 1. if the receive data register is read while there is no valid data, then a fifo underrun condition occurs. the underrun condition is reflected in the status register by forcing all bits to logic zero on the first status register read
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 141 immediately following the received data register read which caused the underrun condition.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 142 register 03bh, 0bbh, 13bh, 1bbh: rfdl receive data bit type function default bit 7 r rd7 x bit 6 r rd6 x bit 5 r rd5 x bit 4 r rd4 x bit 3 r rd3 x bit 2 r rd2 x bit 1 r rd1 x bit 0 r rd0 x the rfdl receive data register is filled starting from the msb bit position (rd7) and the data bits are shifted to lower bit positions as more bits are received, with one to eight data bits being valid. the number of valid bits is equal to 1 plus the value of nvb[2:0] from the rfdl status register. an nvb[2:0] value of 111 indicates that rd[7:0] contain valid data bits where rd0 corresponds to the first bit of the serial byte received by the rfdl. these registers are actually 4 level fifos. if data is available, the fe bit in the rfdl status register is low. if intc[1:0] (in the rfdl interrupt control/status register) is set to 01, this register must be read within 31 data bit periods to prevent an overrun. if intc[1:0] is set to 11, this register must be read within 15 data bit periods. when an overrun is detected, an interrupt is generated and the fifo is held cleared until the status register is read. when the lapd abort sequence (01111111) is detected in the data an abort interrupt is generated and the data that has been shifted into the serial to parallel converter is written into the fifo. a read of this register increments the fifo pointer at the end of the read. if this register read causes a fifo underrun, then the pointer is inhibited from incrementing. the underrun condition will be signaled in the next rfdl status register read by returning all zeros.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 143 registers 03ch, 0bch, 13ch and 1bch: interrupt id/clock monitor bit type function default bit 7 r int4 0 bit 6 r int3 0 bit 5 r int2 0 bit 4 r int1 0 bit 3 r btclka 0 bit 2 r tclkia 0 bit 1 r brclka 0 bit 0 r rclkia 0 these registers provide interrupt identification and activity monitoring on equad clocks. the framer which caused the intb output to transition low can be identified by reading register 03ch - the intx bits in register 0bch, 13ch, and 1bch are invalid. the intx bit in register 03ch will be high if the xth framer caused the interrupt. the interrupt source registers of that framer can then be used to find which block within the framer generated the interrupt. when a monitored clock signal makes a low to high transition, the corresponding register bit is set high. the bit will remain high until this register is read, at which point, all the bits in this register are cleared. a lack of transitions is indicated by the corresponding register bit reading low. these registers should be read at periodic intervals to detect clock failures. int4, int3, int2, int1: the intx bit will be high if the xth framer (the framer corresponding to the input pin btclk[x]) caused the intb pin to transition low. btclka: the btclk active (btclka) bit monitors for low to high transitions on the btclk[x] input. btclka is set high on a rising edge of btclk[x], and is set low when this register is read. tclkia: the tclki active (tclkia) bit monitors for low to high transitions on the tclki[x] input. tclkia is set high on a rising edge of tclki[x], and is set low when this register is read.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 144 brclka: the brclk active (brclka) bit monitors for low to high transitions on the brclk input. brclka is set high on a rising edge of brclk, and is set low when this register is read. rclkia: the rclki active (rclka) bit monitors for low to high transitions on the rclki[x] input. rclkia is set high on a rising edge of rclki[x], and is set low when this register is read.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 145 registers 03dh, 0bdh, 13dh and 1bdh: backplane parity configuration and status bit type function default bit 7 r/w btptyp 0 bit 6 r/w btprtye 0 bit 5 r btpcmpi x bit 4 r btsigpi x bit 3 unused x bit 2 unused x bit 1 r/w brptyp 0 bit 0 r/w brprtye 0 these registers provide control and status reporting of data integrity checking on the backplane buses. parity bits in the first bit position of ts0 (henceforth called the prty-bit position) represents parity over the previous frame (excluding the parity bit) for the pcm and sig data streams. brx2rail must be set to logic 0. btptyp: the transmit backplane parity type (btptyp) bit sets even or odd parity in the transmit streams. if btptyp is a logic zero, then the expected parity value in the prty-bit position of btpcm[x] and btsig[x] is even, thus it is a one if the number of ones in the previous frame (excluding the prty-bit) is odd. if btptyp is a logic one, then the expected parity value in the prty-bit position of btpcm[x] and btsig[x] is odd, thus it is a one if the number of ones in the previous frame (excluding the prty-bit) is even. btprtye: the btprtye bit enables transmit parity interrupts. when set a logic one, parity errors on inputs btpcm[x] and btsig[x] are indicated by the btpcmi and btsigi bits, respectively, and by the intb output. when set to logic zero, parity errors are indicated by the btpcmi and btsigi status bits but are not indicated on the intb output.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 146 btpcmi: the btpcmi bit indicates if a parity error has been detected on the btpcm[x] input. this bit is cleared when this register is read. odd or even parity is selected by the btptyp bit. btsigi: the btsigi bit indicates if a parity error has been detected on the btsig[x] input. this bit is cleared when this register is read. odd or even parity is selected by the btptyp bit. brptyp: the receive backplane parity type (brptyp) bit sets even or odd parity in the receive streams. if brptyp is a logic zero, then the parity value in the prty- bit position of brpcm[x] and brsig[x] is even, thus it is a one if the number of ones in the previous frame (excluding the prty-bit) is odd. if brptyp is a logic one, then the parity value in the prty-bit position of brpcm[x] and brsig[x] is odd, thus it is a one if the number of ones in the previous frame (excluding the prty-bit) is even. brptyp only has effect if brprtye is a logic one. brprtye: the brprtye bit enables receive parity insertion. when set a logic one, parity is inserted into the prty-bit position of the brpcm[x] and brsig[x] streams. when set to logic zero, the data in the prty-bit position passes through unaltered.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 147 register 040h, 0c0h, 140h, 1c0h: sigx block configuration bit type function default bit 7 r/w accel 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w mtkc 0 bit 2 r/w reserved 0 bit 1 r/w ind 0 bit 0 r/w pcce 0 this register allows selection of the microprocessor access type, and allows enabling of the per-timeslot configuration registers. accel: the accel bit is used to enable an accelerated test mode for production purposes only. for proper operation the accel bit must be set to logic 0. mtkc: the master trunk conditioning bit, mtkc, enables trunk conditioning for all timeslots, regardless of per-timeslot settings. a logic 1 in the mtkc bit position enables master trunk conditioning. data from all of the timeslot trunk conditioning data registers (40h to 5fh) is output onto the data stream brpcm and the per-timeslot signaling trunk conditioning bits a,b,c and d are output onto the signaling data stream brsig. the mtkc bit is ored with the per-timeslot trunk conditioning enable bits in the per-timeslot configuration registers to form the applied per-timeslot trunk conditioning enables. when the equad is reset, the mtkc bit is set to logic 0, disabling master trunk conditioning. the mtkc bit is independent of the trken bit of the equad receive options register and takes precedence over it. if trken is a logic 1, an out- of-frame condition causes the contents of the elst idle code register to placed in all time slots on brpcm. brsig presents the frozen signaling. if mtkc is a logic 1, each brpcm and brsig time slot may have an unique idle code.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 148 reserved: the reserved bit must be programmed to logic 0 for proper operation. ind: the ind bit controls the microprocessor access type: either indirect or direct. the ind bit must be set to logic 1 for proper operation. when the equad is reset, the ind bit is set low, disabling the indirect access mode. pcce: the pcce bit enables the per-timeslot functions. when the pcce bit is set to a logic 1, data inversion, trunk conditioning and signaling debouncing are performed on a per-timeslot basis. when the pcce bit is set to logic 0, the per-timeslot functions are disabled. upon reset of the equad, the accel, mtkc, ind, and pcce bits are all set to logic 0 disabling p indirect access and per-timeslot functions.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 149 register 041h, 0c1h, 141h, 1c1h: sigx block p access status bit type function default bit 7 r busy 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x busy: the busy bit in the status register is high while a p access request is in progress. the busy bit goes low timed to an internal high-speed clock rising edge after the access has been completed. during normal operation, the status register should be polled until the busy bit goes low before another p access request is initiated. a p access request is typically completed within 480 ns.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 150 register 042h, 0c2h, 142h, 1c2h: sigx block time slot indirect address/control bit type function default bit 7 r/w r/wb x bit 6 r/w a6 x bit 5 r/w a5 x bit 4 r/w a4 x bit 3 r/w a3 x bit 2 r/w a2 x bit 1 r/w a1 x bit 0 r/w a0 x this register allows the p to access to internal sigx registers addressed by the a[6:0] bits and perform the operation specified by the r/wb bit. writing to this register with a valid address and r/wb bit initiates an internal p access request cycle. the r/wb bit selects the operation to be performed on the addressed register: when r/wb is set to a logic 1, a read from the internal sigx register is requested, when r/wb is set to a logic 0, a write to the internal sigx register is requested.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 151 register 043h, 0c3h, 143h, 1c3h: sigx block time slot indirect data buffer bit type function default bit 7 r/w d[7] x bit 6 r/w d[6] x bit 5 r/w d[5] x bit 4 r/w d[4] x bit 3 r/w d[3] x bit 2 r/w d[2] x bit 1 r/w d[1] x bit 0 r/w d[0] x in the case of an indirect write, the indirect data register holds the value that will be written to the desired register when a write is initiated via the timeslot indirect address register. in the case of an indirect read, the indirect data register will hold the contents of the indirectly addressed register, when the read has been completed. please refer below to the per-timeslot register descriptions for the expected bit formats. the signaling and per-timeslot functions are allocated within the registers as follows: 21h signaling data register for time slot 1 22h signaling data register for time slot 2 ?? ?? ?? 2fh signaling data register for time slot 15 31h signaling data register for time slot 17 ?? ?? ?? 3eh signaling data register for time slot 30
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 152 3fh signaling data register for time slot 31 40h pcm trunk conditioning byte for time slot 0 41h pcm trunk conditioning byte for time slot 1 ?? ?? ?? 5eh pcm trunk conditioning byte for time slot 30 5fh pcm trunk conditioning byte for time slot 31 60h configuration and signaling trunk conditioning data for time slot 0 61h configuration and signaling trunk conditioning data for time slot 1 ?? ?? ?? 7eh configuration and signaling trunk conditioning for time slot 30 7fh configuration and signaling trunk conditioning for time slot 31
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 153 sigx indirect registers 33 (21h)- 47 (2fh) - segment 2: typical timeslot signaling data register (tss 1-15) bit type function default bit 7 r a ts n+16 x bit 6 r b ts n+16 x bit 5 r c ts n+16 x bit 4 r d ts n+16 x bit 3 r a ts n x bit 2 r b ts n x bit 1 r c ts n x bit 0 r d ts n x
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 154 sigx indirect registers 49 (31h)- 63 (3fh) - segment 2: typical timeslot signaling data register (tss 17-31) bit type function default bit 7 r a ts n-16 x bit 6 r b ts n-16 x bit 5 r c ts n-16 x bit 4 r d ts n-16 x bit 3 r a ts n x bit 2 r b ts n x bit 1 r c ts n x bit 0 r d ts n x
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 155 sigx indirect registers 64 (40h) - 95 (5fh) - segment 3: typical per-timeslot pcm trunk conditioning data register bit type function default bit 7 r/w tcd[7] x bit 6 r/w tcd[6] x bit 5 r/w tcd[5] x bit 4 r/w tcd[4] x bit 3 r/w tcd[3] x bit 2 r/w tcd[2] x bit 1 r/w tcd[1] x bit 0 r/w tcd[0] x when trunk conditioning is enabled, pcm trunk conditioning bits tcd[7:0] replace timeslot bits 1 through 8 respectively for the referenced timeslot. ts0 and ts16 can be replaced with trunk conditioning data.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 156 10.1 sigx indirect registers 96 (60h) - 127 (7fh) - segment 4: typical per-timeslot configuration and signaling trunk conditioning data register bit type function default bit 7 r/w rinv[1] x bit 6 r/w rinv[0] x bit 5 r/w rtkce x bit 4 r/w rdebe x bit 3 r/w a x bit 2 r/w b x bit 1 r/w c x bit 0 r/w d x rinv[1:0]: the rinv[1:0] bits select whether the output brpcm stream is entirely or selectively inverted. the bit mapping is as follows. 00 - do not invert 01 - invert even bits (2,4,6,8) 10 - invert odd bits (1,3,5,7) 11 - invert all bits rtkce: the rtkce bit enables per-timeslot data stream and signal stream trunk conditioning. a logic 1 in this bit position enables trunk conditioning while a logic 0 disables trunk conditioning. when rtkce is enabled, per-timeslot trunk conditioning data from one of the timeslot trunk conditioning data registers (one of 40h to 5fh) is output onto the data stream, brpcm. in addition, the per-timeslot signaling trunk conditioning bits a,b,c and d are output onto the signaling data stream, brsig.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 157 rdebe: the rdebe bit enables debouncing of timeslot signaling bits. a logic 1 in this bit position enables signaling debouncing while a logic 0 disables it. when debouncing is selected, per-timeslot signaling transitions are ignored until two consecutive, equal values are sampled. a,b,c and d: a,b,c and d are the per-timeslot signaling trunk conditioning bits. when trunk conditioning is enabled, these bits are used as signaling data, instead of the extracted timeslot signaling bits, and are output onto the brsig output. to enable the rinv[1:0], rtkce and rdebe bits, the pcce bit in the sigx configuration register must be set to logic 1. when these bits are enabled, bits rinv[1:0] and rdebe are ored with their primary input equivalents to generate the applied configuration signals.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 158 register 044h, 0c4h, 144h, 1c4h: tran configuration bit type function default bit 7 r/w ami 0 bit 6 r/w sigen 1 bit 5 r/w dlen 1 bit 4 r/w gencrc 0 bit 3 r/w fdis 0 bit 2 r/w febedis 0 bit 1 r/w indis 0 bit 0 r/w xdis 0 ami: the ami bit enables ami line coding when set to logic 1; when it is set to logic 0, the hdb3 line coding is enabled. sigen, dlen: the sigen and dlen bits select the signaling data source for time slot 16 (ts16) as follows: sigen dlen mode 0 0 signaling insertion disabled. ts16 data is taken directly from the input btpcm[x] ts16. 0 1 ccs enabled. ts16 data is taken directly from the tdlsig[x] input or from the hdlc/lapd transmitter. 1 0 reserved. 1 1 cas enabled. ts16 data is taken from either btsig[x] stream or from the tpsc data control byte as selected on a per-timeslot basis via the sigsrc bit. the format of the btsig[x] input data stream is shown in the "functional timing" section.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 159 when channel associated signaling (cas) is enabled, the format of the input btsig stream is selected by the dlen bit. a logic 1 in the dlen bit position selects the pmc compatible format in which the btsig stream contains the signaling data nibble in the lower four bits of the time slot byte. a logic 0 in the dlen bit position is reserved and should not be used. gencrc: the gencrc bit enables generation of the crc multiframe when set to logic 1. when enabled, the tran generates the crc multiframe alignment signal, calculates and inserts the crc bits, and if enabled by febedis, inserts the febe indication in the spare bit positions. the crc bits transmitted during the first sub-multiframe (smf) are indeterminate and should be ignored. the crc bits calculated during the transmission of the 'n'th smf (smf n) are transmitted in the following smf (smf n+1). when gencrc is set to logic 0, the crc generation is disabled. the crc bits are then set to the logic value contained in the si[1] bit position in the international/national bit control register and bit 1 of the nfas frames are set to the value of si[0] bit if enabled by indis, or, if not enabled by indis, are taken directly from btpcm[x]. when btpcm[x] or si[1] are transmitted in lieu of the calculated crc bits, there is no delay of one smf (i.e., the btpcm[x] bits received in smf n are transmitted in the same smf). the same applies when substituting si[1] in place of the calculated crc bits. fdis: the fdis bit value controls the generation of the framing alignment signal. a logic 1 in the fdis bit position disables the generation of the framing pattern in ts0 and allows the incoming data on btpcm[x] to pass through the tran transparently. a logic 0 in fdis enables the generation of the framing pattern, replacing ts0 of frames 0,2,4,6,8,10,12,14 with the frame alignment signal, and if enabled by indis, replacing ts0 of frames 1,3,5,7,9,11,13,15 with the contents of the international/national bits control register. when fdis is a logic 1, framing is globally disabled and the values in controls bits gencrc, febedis, indis, and xdis are ignored. note that the above is true only if the ais bit in the tran transmit alarm/diagnostic control register is a logic 0. if ais is logic 1, the output bit stream becomes all ones unconditionally. indis, gencrc and febedis: the indis bit controls the insertion of the international and national bits into ts0. when indis is set to logic 0, the contents of the tran international/national bit control register are inserted into ts0; when indis
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 160 is a logic 1, the contents of the tran international/national bit control register are ignored and the values for those bit positions in the output stream are taken directly from the btpcm[x] stream. when indis and fdis are logic 0, the bit values used for the international and national bits are dependent upon the values of the gencrc and febedis configuration bits, as shown in the following table: gencrc febedis source of international/national bits 0 x bit position si[1] in the international/national control register is used for the international bit in the frame alignment signal (fas) frames and the si[0] bit in the non-frame alignment signal (nfas) frames if indis is logic 0. tpcm replaces si[1:0] if indis is logic 1. bit positions sn[4:0] in the register are used for the national bits in nfas frames. 1 0 the calculated crc bits are used for the international bit in the fas frames and the generated crc multiframe alignment signal and the febe bits are used for the international bit in the nfas frames. bit positions sn[4:0] in the tran international/national control register are used for the national bits in nfas frames. 1 1 the calculated crc bits are used for the international bit in the fas frames and the generated crc multiframe alignment signal is used for the international bit in the nfas frames, with the si[1:0] bits in the international/national control register used for the spare bits. bit positions sn[4:0] in the register are used for the national bits in nfas frames. xdis: if fdis is logic 0 and sigen is logic 1, the xdis bit controls the insertion of the extra bits in ts16 of frame 0 of the signaling multiframe as follows. when xdis is set to a logic 0, the contents of the tran extra bits control register are inserted into ts16, frame 0; when xdis is a logic 1, the contents of the register are ignored and the values for those bits positions in the output
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 161 stream are taken directly from the btpcm[x] stream. i.e., when xdis and fdis are logic 0, and sigen is logic 1, the x1,x3,x4 bit values from the tran extra bits control register are used for the extra bits in ts16 of frame 0 of the signaling multiframe. when the equad is reset, the contents of this register are set to logic 0, except sigen and dlen which are set to logic 1.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 162 register 045h, 0c5h, 145h, 1c5h: tran transmit alarm/diagnostic control bit type function default bit 7 r/w mtrk 0 bit 6 r/w fpatinv 0 bit 5 r/w splrinv 0 bit 4 r/w spatinv 0 bit 3 r/w remais 0 bit 2 r/w mfais 0 bit 1 r/w ts16ais 0 bit 0 r/w ais 0 mtrk: the mtrk bit forces trunk conditioning (i.e., idle code substitution and signaling substitution) when mtrk is a logic 1. this has the same effect as setting data substitution to idle code on time slots 1-15 and 17-31 (setting bits subs and ds[0] to binary 10 in time slots 1-15 and 17-31) and sourcing the signaling data from the tpcsc stream, if sigen is logic 1. when sigen is logic 0, ts16 will be treated the same as time slots 1-15 and 17-31 and will contain data sourced from tidl. ts0 data is determined by the control bits associated with it and is independent of the value of mtrk. f pat i n v: the fpatinv bit is a diagnostic control bit. when set to logic 1, fpatinv forces the frame alignment signal (fas) written into ts0 to be inverted (i.e., the correct fas, 0011011, is substituted with 1100100); when set to logic 0, the fas is unchanged. splrinv: the splrinv bit is a diagnostic control bit. when set to logic 1, splrinv forces the "spoiler bit" written into bit 2 of ts0 of nfas frames to be inverted (i.e., the spoiler bit is forced to 0); when set to logic 0, the spoiler bit is unchanged. s pat i n v: the spatinv bit is a diagnostic control bit. when set to logic 1, spatinv forces the signaling multiframe alignment signal written into bits 1-4 of ts16
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 163 of frame 0 of the signaling multiframe to be inverted (i.e., the correct signaling multiframe alignment signal, 0000, is substituted with 1111); when set to logic 0, the signaling multiframe alignment signal is unchanged. remais: the remais bit controls the transmission of the remote alarm indication signal. a logic 1 in the remais bit position causes bit 3 of nfas frames to be forced to logic 1; otherwise, bit 3 of nfas frames is a logic 0. mfais: the mfais bit controls the transmission of the signaling multiframe alarm indication signal. a logic 1 in the mfais bit position causes the y-bit (bit 6) of ts16 of frame 0 of the signaling multiframe to be forced to logic 1; otherwise, the y-bit is a logic 0. ts16ais: the ts16ais bit controls the transmission of the time slot 16 alarm indication signal (all-ones in ts16). a logic 1 in the ts16ais bit position forces ts16 of all frames in the output stream to logic 1. ais: the ais bit controls the transmission of the alarm indication signal (unframed all-ones). a logic 1 in the ais bit position forces the output streams to logic 1. when the equad is reset, the contents of this register are set to logic 0.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 164 register 046h, 0c6h, 146h, 1c6h: tran international/national control bit type function default bit 7 r/w si[1] 1 bit 6 r/w si[0] 1 bit 5 unused x bit 4 r/w sn[4] 1 bit 3 r/w sn[3] 1 bit 2 r/w sn[2] 1 bit 1 r/w sn[1] 1 bit 0 r/w sn[0] 1 sn[4:0]: bits 4 to 0 of this register are substituted in bit positions 4 to 8, respectively, of ts0 of each nfas frame when framing generation (fdis = 0) and international/national bit control (indis = 0) is enabled. when fdis or indis is logic 1, the contents of this register are ignored and replaced with the values received on the btpcm[x] input. the bits sn[4:0] correspond to the 5 national bits; these can be programmed to any value and are inserted into the national bit positions in the nfas frames when enabled by indis. si[1:0]: the bits si[1] and si[0] correspond to the international bits. the si[1] and si[0] bits can be programmed to any value and will be inserted into bit 1 of each fas frame and nfas frame, respectively, when the block is configured for frame generation, indis is set to logic 0, and crc multiframe generation is disabled. when crc multiframe generation is enabled, both si[1] and si[0] are ignored if febe indication is enabled; if febedis is a logic 1 and indis = 0, the values programmed in the si[1] and si[0] bit positions are inserted into the spare bit locations of frame 13 and frame 15, respectively, of the crc multiframe. if both febedis and indis are logic 1, then data from btpcm[x] replaces the si[0] and si[1] bits in the crc multiframe. the si[1], si[0], and sn[4:0] bits should be programmed to a logic 1 when not being used to carry information.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 165 when the equad is reset, the contents of the register are set to logic 1.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 166 register 047h, 0c7h, 147h, 1c7h: tran extra bits control bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w x[1] 1 bit 2 unused x bit 1 r/w x[3] 1 bit 0 r/w x[4] 1 x[4:3,1]: the x[1], x[3], and x[4] bits control the value programmed in the x[1], x[3], and x[4] bit locations (bits 5,7, and 8) in ts16 of frame 0 of the signaling multiframe, when enabled by xdis. the x[1], x[3], and x[4] bits should be programmed to a logic 1 when not being used to carry information. when the equad is reset, the contents of the register are set to logic 1.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 167 register 048h, 0c8h, 148h, 1c8h: pmon control/status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w inte 0 bit 1 r xfer 0 bit 0 r ovr 0 this register contains status information indicating when counter data has been transferred into holding registers and indicating whether the holding registers have been overrun. configuration for pmon interrupt enable is also available in this register. inte: the inte bit controls the generation of a microprocessor interrupt when the transfer clock has caused the counter values to be stored in the holding registers. a logic 1 bit in the inte position enables the generation of an interrupt ; a logic 0 bit in the inte position disables the generation of an interrupt. xfer: the xfer bit indicates that a transfer of counter data has occurred. a logic 1 in this bit position indicates that a latch request, initiated by writing to one of the counter register locations, was received and a transfer of the counter has occurred. a logic 0 indicates that no transfer has occurred. the xfer bit is cleared (acknowledged) by reading this register. ovr: the ovr bit is the overrun status of the holding registers. a logic 1 in this bit position indicates that a previous interrupt has not been acknowledged before the next transfer clock has been issued and that the contents of the holding registers have been overwritten. a logic 0 indicates that no overrun has occurred. the ovr bit is cleared by reading this register.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 168 10.2 registers 049-04fh, 0c9h-0cfh, 149h-14fh, 1c9h-1cfh: latching performance data all the performance data registers in one framer are updated as a group by writing to any of the pmon block count registers (addresses 049h-04fh for framer 1, 0c9h-0cfh for framer 2, 149h-14fh for framer 3, and 1c9h-1cfh for framer 4). a write to any one of these locations loads performance data in the associated pmon block into the internal holding registers (it is necessary to write to one, and only one, count register address to latch all the count data register values into the holding registers and to reset all the counters for each polling cycle for the associated framer). alternately, the performance data registers for all four framers are updated by writing to the revision/chip id/global pmon update register (address 00ch). the data contained in the holding registers can then be subsequently read by microprocessor accesses into the pmon block count register address space. the latching of count data, and subsequent resetting of the counters, is synchronized to the internal event timing so that no events are missed. the pmon is loaded with new performance data within 3.5 recovered clock periods of the latch performance data register write. with nominal line rates, the pmon registers should not be polled until 1.71sec have elapsed from the "latch performance data" register write. when the equad is reset, the contents of the pmon count registers are unknown until the first latching of performance data is performed.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 169 register 049h, 0c9h, 149h, 1c9h: framing bit error count bit type function default bit 7 unused x bit 6 r fer[6] x bit 5 r fer[5] x bit 4 r fer[4] x bit 3 r fer[3] x bit 2 r fer[2] x bit 1 r fer[1] x bit 0 r fer[0] x this register indicates the number of framing bit error events that occurred during the previous accumulation interval. the fer counts are suppressed when the frmr has lost frame alignment (oof in the frmr framing status register is set).
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 170 register 04ah, 0cah, 14ah, 1cah: far end block error count lsb bit type function default bit 7 r febe[7] x bit 6 r febe[6] x bit 5 r febe[5] x bit 4 r febe[4] x bit 3 r febe[3] x bit 2 r febe[2] x bit 1 r febe[1] x bit 0 r febe[0] x
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 171 register 04bh, 0cbh, 14bh, 1cbh: far end block error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r febe[9] x bit 0 r febe[8] x these registers indicate the number of far end block error events that occurred during the previous accumulation interval. the febe counts are suppressed when the frmr has lost frame alignment (oof in the frmr framing status register is set).
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 172 register 04ch, 0cch, 14ch, 1cch: crc error count lsb bit type function default bit 7 r crce[7] x bit 6 r crce[6] x bit 5 r crce[5] x bit 4 r crce[4] x bit 3 r crce[3] x bit 2 r crce[2] x bit 1 r crce[1] x bit 0 r crce[0] x
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 173 register 04dh, 0cdh, 14dh, 1cdh: crc error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r crce[9] x bit 0 r crce[8] x these registers indicate the number of crc error events that occurred during the previous accumulation interval. crc error events are suppressed when the frmr is out of crc-4 multiframe alignment (oocmf bit in the frmr framing status register is set).
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 174 register 04eh, 0ceh, 14eh, 1ceh: line code violation count lsb bit type function default bit 7 r lcv[7] x bit 6 r lcv[6] x bit 5 r lcv[5] x bit 4 r lcv[4] x bit 3 r lcv[3] x bit 2 r lcv[2] x bit 1 r lcv[1] x bit 0 r lcv[0] x
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 175 register 04fh, 0cfh, 14fh, 1cfh: line code violation count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r lcv[12] x bit 3 r lcv[11] x bit 2 r lcv[10] x bit 1 r lcv[9] x bit 0 r lcv[8] x these registers indicate the number of lcv error events that occurred during the previous accumulation interval. an lcv event is defined as the occurrence of a bipolar violation or excessive zeros. the counting of excessive zeros can be disabled by the bpv bit of the receive interface configuration register.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 176 11 test features description simultaneously asserting the csb, rdb and wrb inputs causes all output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the equad. test mode registers (as opposed to normal mode registers) are mapped into addresses 200h-3ffh. test mode registers may also be used for board testing. when all of the constituent telecom system blocks within the equad are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "test mode 0" for details). notes on test mode register bits: 1. writing values into unused register bits has no effect. reading unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2. writeable test mode register bits are not initialized upon reset unless otherwise noted. 11.1 test mode 0 in test mode 0, the equad allows the logic levels on the device inputs to be read through the microprocessor interface, and allows the device outputs to be forced to either logic level through the microprocessor interface. to enable test mode 0, the iotst bit in the test mode select register is set to logic 1 and the following addresses must be written with 00h: 211h, 219h, 21dh, 221h, 231h, 235h, 239h, 241h, 245h, 291h, 299h, 29dh, 2a1h, 2b1h, 2b5h, 2b9h, 2c1h, 2c5h, 311h, 319h, 31dh, 321h, 331h, 335h, 339h, 341h, 345h, 391h, 399h, 39dh, 3a1h, 3b1h, 3b5h, 3b9h, 3c1h, and 3c5h. also, to enable input and output signals to propagate through the interface blocks, the value 00h must be written to addresses 001h, 002h, 003h, 004h, 081h, 082h, 083h, 084h, 101h, 102h, 103h, 104h, 181h, 182h, 183h, and 184h. the value 02h must be written to addresses 007h, 087h, 107h, and 187h. reading the following address locations returns the values for the indicated inputs :
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 177 ta bl e 4 - addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 210h rdp[1] rdn[1] rclki[1] 218h xclk tclki[1] 21ch brfpi brclk 244h [1] btpcm btsig[1] tdlsig[1] 246h menb btfp[1] btclk[1] 290h rdp[2] rdn[2] rclki[2] 298h xclk tclki[2] 29ch brfpi brclk 2c4h btpcm[2] btsig[2] tdlsig[2] 2c6h menb btfp[2] btclk[2] 310h rdp[3] rdn[3] rclki[3] 318h xclk tclki[3] 31ch brfpi brclk 344h btpcm[3] btsig[3] tdlsig[3] 346h menb btfp[3] btclk[3] 390h rdp[4] rdn[4] rclki[4] 398h xclk tclki[4] 39ch brfpi brclk 3c4h btpcm[4] btsig[4] tdlsig[4] 3c6h menb btfp[4] btclk[4] writing the following address locations forces the outputs to the value in the corresponding bit position: ta bl e 5 - addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 210h intb 1 rclko[1] 212h brpcm[1], brsig[1] mrd 218h intb 1 tclko[1] tdn[1] tdp[1] 21ch intb 1 220h rfp[1] 223h intb 1
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 178 addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 238h rdlclk[1] rdlsig[1] 240h brfpo[1] 244h tdlclk[1] 290h intb 1 rclko[2] 292h brpcm[2] brsig[2] 298h intb 1 tclko[2] tdn[2] tdp[2] 29ch intb 1 2a0h rfp[2] 2a3h intb 1 2b8h rdlclk[2] rdlsig[2] 2c0h brfpo[2] 2c4h tdlclk[2] 310h intb 1 rclko[3] 312h brpcm[3] brsig[3] 318h intb 1 tclko[3] tdn[3] tdp[3] 31ch intb 1 320h rfp[3] 323h intb 1 338h rdlclk[3] rdlsig[3] 340h brfpo[3] 344h tdlclk[3] 390h intb 1 rclko[4] 392h brpcm[4] brsig[4] 398h intb 1 tclko[4] tdn[4] tdp[4] 39ch intb 1 3a0h rfp[4] 3a3h intb 1 3b8h rdlclk[4] rdlsig[4] 3c0h brfpo[4] 3c4h tdlclk[4]
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 179 notes: 1. writing a logic 1 to any of the block interrupt signals asserts the intb output low.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 180 12 functional timing figure 9 - ts16 receive datalink interface rdlsig[x] rdlclk[x] rfp[x] bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 data from time slot 16 extracted and output serially over the subsequent 32 time slots 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 2 3 4 5 6 7 089 10 11 12 13 14 15 16 17 time slots when ts16 is selected as the source of the receive datalink (rxdmasig=0 and all of rxsaxen=0), the 64 kbit/s ts16 data is presented on rdlsig[x] with an accompanying rdlclk[x] with a period of 4 time slots. the data on rdlsig[x] is generated on the falling edge of rdlclk[x]. for the rfp timing shown above, the srsmfp and srcmfp register bits are set to logic 0. figure 10 - ts0 receive datalink interface rclko[x] rfp[x] timeslot 1 nfas, timeslot 0 rdlclk[x] fas, timeslot 1 rdlsig[x] 4 undefined undefined 56 78 1 78 78 67 12 345 6 78 8 12 34 5 12 34 12 3 45 678 52 when ts0 is selected as the source of the receive datalink (rxdmasig=0 and at least one rxsaxen bit is a logic 1), the national use bit of ts0 of the nfas frames data is presented on rdlsig[x] with an accompanying rdlclk[x]. a clock pulse is generated on rdlclk[x] for each national use bit on rdlsig[x] which has the associated enable (rxsaxen, x=4 to 8) set to logic 1. depending on the settings of the rxsaxen bits, the effective bit rate of the data link may
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 181 range between 4 bit/s and 20 kbit/s. rdlsig[x] is generated on the falling edge of rdlclk[x]. for the diagram shown above, the srsmfp and srcmfp register bits are set to logic 0. the timing with respect to rclko[x] shown here is valid only if the rclkosel bit is set to logic 0. figure 11 - ts16 transmit datalink interface tdlclk[x] tdlsig[x] tdp/tdd[x] tdn[x] bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 12 34 567 0 8 9 10111213141516 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 14 time slots btpcm[x] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 234 567 0 8 9 1011 121314 1516 17 ccs data collected over 32 timeslots and inserted into ts16 when common channel signaling (ccs) data sourced from tdlsig[x] is selected (dlen=1, sigen=0 and txdmasig=0), tdlclk[x] is active, producing one cycle every 4 time slots, aligned to the incoming btpcm[x]. the data on tdlsig[x] is sampled on the rising edge of tdlclk[x] and put directly into ts16 on the outgoing data stream. figure 12 - ts0 transmit datalink interface btclk[x] btpcm[x] timeslot 31 1 78 78 67 123 45 8 1 2 3 4 5 6 78123 4 12 3 456 78 nfas, timeslot 0 fas, timeslot 0 52 tdlclk[x] tdlsig[x] don't care don't care 45678 when the ts0 maintenance datalink is active (dlen=0 or sigen=1, txdmasig=0, at least one txsaxen bit is a logic 1), the data presented on tdlsig[x] is inserted into the national use bits of the nfas frames. a clock pulse is generated on tdlclk[x] for each national use bit on tdlsig[x] which has the associated enable (txsaxen, x=4 to 8) set to logic 1. if the enable is
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 182 logic 0, the specific bit value is sourced from the tran block international/national control register. depending on the settings of the txsaxen bits, the effective bit rate of the data link may range between 4 bit/s and 20 kbit/s. tdlsig[x] is sampled on the rising edge of tdlclk[x]. note that the tdlsig[x] data is shifted from the corresponding btpcm[x] data by 2 bits. 12.1 receive backplane interface figure 13 - rohm=0, brx2rail=0, brxsmfp=0 and brxcmfp=0 123456 78 ab cd 123456 78123456 78 ab cd 12 34567812 345678 abcd timeslot 31 timeslot 0 timeslot 1 timeslot 16 timeslot 17 brclk brfpo[x] brpcm[x] brsig[x] brfpi undefined undefined undefined the receive backplane is configured to generate 2048 kbit/s, single-rail formatted data with frame alignment indication. the receive backplane options register is programmed to brx2rail=0, brxsmfp=0 and brxcmfp=0. the brfpi input pulse need not exist every frame; only one is required to align the backplane signals. if no brfpi pulse has been presented since reset, the outputs will assume an arbitrary alignment. if rohm=0, brxsmfp=0 and brxcmfp=1, the brfpo[x] signal pulses high only during the first bit of the first frame in the crc multiframe. if rohm=0, brxsmfp=1 and brxcmfp=0, the brfpo[x] signal pulses high only during the first bit of the frame containing the signaling multiframe alignment signal.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 183 figure 14 - receive composite multiframe output (brxsmfp=1 and brxcmfp=1) 123456 78 ab cd 123456 78 timeslot 31 timeslot 0 brclk brfpo[x] brpcm[x] brsig[x] brfpi undefined undefined 12 345678 abcd c1 2 345678 timeslot 31 timeslot 0 undefined undefined if rohm=0, brxsmfp=1 and brxcmfp=1, the brfpo[x] signal becomes high on the falling brclk edge marking the beginning of bit 1 of frame 1 of every 16 frame signaling multiframe and returns low on the falling brclk edge marking the end of bit 1 of frame 1 of every 16 frame crc multiframe. figure 15 - receive overhead output (rohm=1) 123456 78 ab cd 123456 78123456 78 ab cd 12 34567812 345678 abcd timeslot 31 timeslot 0 timeslot 1 timeslot 16 timeslot 17 brclk brfpo[x] brpcm[x] brsig[x] brfpi undefined undefined undefined if the rohm bit is logic 1, the brfpo[x] signal marks the overhead by becoming high during timeslots 0 and 16, as in figure 15.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 184 figure 16 - elstbyp=1, srsmfp=1, srcmfp=1, brxsmfp=1, brxcmfp=0 123456 78 ab cd 123456 78123456 78 abcd 123456 7812 3456 78 timeslot 31 timeslot 0 timeslot 1 timeslot 31 timeslot 0 rclko[x] brfpo[x] brpcm[x] brsig[x] rfp[x] undefined undefined undefined abcd undefined the receive backplane is configured to generate single-rail formatted data with frame alignment indication and with the elst bypassed (elstbyp=1). the receive options register is programmed to srsmfp=1 and srcmfp=1, the receive backplane options register is programmed to brxsmfp=1 and brxcmfp=0. in this case, the backplane output signals are timed off of the output clock rclko[x] instead of the input clock brclk. rfp marks (though offset by 3 bits) the start of each signaling multiframe, and the start of each crc multiframe. figure 17 - receive channel interface rclko[x] rdlsig[x] 1 2 345678 12 345678 1 2 345678 1 23456 7 8 123456 78 timeslot 31 timeslot 0 timeslot 1 timeslot 31 timeslot 0 rfp[x] rdlclk[x] don't care don't care the rfrace1 bit in the datalink options register is set to logic 1. the ch[1] and ch[31] register bits in the channel select registers are set to logic 1 and the ch[0] register bit is set to logic 0. channels 1 and 31 are presented on rdlsig[x]. rdlclk[x] is gapped so that it is only active for the channels with the associated ch[x] bit set. as shown here, the srcmfp and srsmfp bits in the receive options register are set to logic 0.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 185 figure 18 - transmit backplane interface 12 345678 abcd 12 34567812 345678 abcd 123456 78123456 78 ab cd timeslot 31 timeslot 0 timeslot 1 timeslot 16 timeslot 17 btclk[x] btpcm[x] btsig[x] btfp[x] don't care don't care don't care the transmit backplane is configured to receive 2048 kbit/s, single-rail formatted data with frame alignment indication. the transmit backplane options register is programmed to btxclk=0, btx2rail=0, btxmfp=0. (if btxmfp=1, the btfp[x] input must be brought high to mark bit 1 of frame 1 of every 16 frame signaling multiframe and brought low following bit 1 of frame 1 of every 16 frame crc multiframe. this mode allows both multiframe alignments to be independently controlled using the single btfp[x] signal. note that if the signaling and crc multiframe alignments are coincident, btfp[x] must pulse high for 1 btclk[x] cycle every 16 frames. figure 19 - transmit channel interface btclk[x] tdlsig[x] 1 2 34 5678 123456 78 1 23456 78 timeslot 31 timeslot 0 timeslot 1 timeslot 31 timeslot 0 btfp[x] tdlclk[x] btpcm[x] 1 2345 6781 234 56781 2345 67 8 1234 56781 234 5678 don't care don't care the tfrace1 bit in the datalink options register is set to logic 1. the ch[1] and ch[31] register bits in the channel select registers are set to logic 1 and the ch[0] register bit is set to logic 0. tdlclk[x] is gapped so that it is only active for the channels with the associated ch[x] bit set. data for channels 1 and 31 are expected on tdlsig[x].
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 186 figure 20 - multiplexed receive backplane interface s a6 s a7 s a8 s a7 s a7 s a7 s a8 s a8 s a8 parity bits may replace these bits bit type framer # si 4 si : international bit u: undefined bit 1: logic 1 bit a: remote alarm indication sa x : national bit x si 1 u 1 si 22 si 3 3 si 44 1 11 1 2 2 1 3 3 1 4 4 a mrclk mrd u u u u u u u 3 3 4 4 1 1 2 23 3 44 1 1 2 2 3 3 4 u 4 s a6 u 1 1 u 1 1 2 u 2 1 3 u 3 1 4 u 4 2 1 u 1 2 2 u 2 2 3 u 3 2 4 u 4 3 1 6 3 b 3 6 4 b 4 7 c 7 c 7 c 7 c 8 d 8 d 8 d 8 d 4 mrclk mrd timeslot 1 timeslot 0 timeslot 31 1 mrd mrfpi mrclk 1 signalling bit bit # framer # u u u u u u u u 11 22 3 3 4 4 1 1 2233 4 4 u 2
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 187 the receive backplane is configured to generate bit interleaved 16.384mhz data. pcm and signaling for all four receivers are presented on a single pin, mrd. the superscripts represent the index of the particular e1 stream. the receive backplane options register for each receiver is programmed to brx2rail=0 and the menb input is low. the preceding figure shows the expected outputs if all four e1 framers are outputting nfas frames. if the brptype bit in the backplane parity configuration and status register is set to logic 1, the backplane receive parity is enabled. the international bit (si bit) of the pcm data stream in each frame is replaced by the parity value calculated over the previous frame (not counting the parity bit of the previous frame). the parity bit of each sig stream follows the parity bit of the pcm data stream.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 188 figure 21 - multiplexed transmit backplane interface s a6 s a7 s a8 s a7 s a7 s a7 s a8 s a8 s a8 parity bits (optional) bit type framer # si 4 si : international bit x: don't care 1: logic 1 bit a: remote alarm indication sa x : national bit x si 1 x 1 si 22 si 3 3 si 44 1 11 1 2 1 3 3 1 4 4 a mtclk mtd x x x 2 x x x x 3 3 4 4 1 1 2 23 3 44 1 1 2 2 3 3 4 x 4 s a6 x 1 1 x 1 1 2 x 2 1 3 x 3 1 4 x 4 2 1 x 1 2 2 x 2 2 3 x 3 2 4 x 4 3 1 6 3 b 3 6 4 b 4 7 c 7 c 7 c 7 c 8 d 8 d 8 d 8 d 4 mtclk mtd timeslot 1 timeslot 0 timeslot 31 1 mtd mtfp mtclk 1 signalling bit bit # framer # x x x x x x x x 11 22 3 3 4 4 1 1 2233 4 4 x 2
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 189 the transmit backplane is configured to expect bit interleaved 16.384mhz data. pcm and signaling for all four receivers are presented on a single pin, mtd. the superscripts represent the index of the particular e1 stream. the transmit backplane options register for each receiver is programmed with brx2rail=0. for input frame pulses shown in the preceding figure, btxmfp=0. the menb input is low. note that in normal operation, where the tran block inserts all the ts0 overhead, the pcm inputs on mtd are "don't cares" for ts0 and ts16. the preceding diagram shows the ts0 bits for timing reference purposes only. if the backplane transmit parity is enabled, the international bit (si bit) position of the pcm data stream in each frame should contain the pcm parity bit. the parity bit of each sig stream follows the parity bit of the pcm data stream. in the case where menb=0 and btxmfp=1, the input mtfp marks the start of the signaling multiframe and the start of the crc multiframe as described in the description of the transmit backplane options register. the waveforms for this case are shown in fig. 21.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 190 figure 22 - multiplexed transmit backplane interface with btxmfp=1 x x mtc lk mt d 3 1 2 2 3 3 1 1 1 25 6 3 25 6 4 25 6 4 25 6 1 x mt fp start of sign all ing mul tif ram e 1 1 x 1 1 2 x 2 1 3 x 3 1 4 x 4 2 1 x 1 2 2 x 2 2 3 x 3 2 4 x 4 3 1 6 3 b 3 6 4 b 4 7 c 7 c 7 c 7 c 8 d 8 d 8 d 8 d 4 mtc lk mt d time slot 0 time slo t 31 mt d mt fp mtc lk 1 sig nal ling bi t bit # framer # 1 1 2 2 3 3 4 4 1 1 2 2 3 3 4 4 time slot 1 time slot 0 time slo t 31 time slot 1 start of crc m ulti fram e
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 191 13 operation after a system reset (either via the rstb pin or via the reset register bit), the equad will default to the following settings: table 6 - configuring the equad from reset setting receiver section transmitter section framing format basic g.704 without crc multiframe. channel associated signaling is enabled. basic g.704 without crc multiframe. channel associated signaling is enabled. line code hdb3 hdb3 e1 interface ? pins rdp/rdd[x] and rdn/rlcv[x] active as digital inputs rdp[x] and rdn[x] ? tdp[x], tdn[x] outputs nrz data updated on falling tclko[x] edge system backplane ? brpcm[x], brsig[x] active ? brfpo[x] indicates frame pulses ? btpcm[x] active ? btsig[x] inactive ? btfp[x] indicates frame alignment data link ? internal rfdl disabled ? rdlsig[x] and rdlclk[x] outputs present the sa4 bit of ts0. ? internal xfdl disabled ? tdlclk[x] output, tdlsig[x] input inserted into sa4 bit of ts0. options ? elst not bypassed ? rfp[x] indicates frame pulses ? timing options not applicable ? digital jitter attenuation enabled, with tclko[x] referenced to btclk[x] diagnostics ? all diagnostic modes disabled ? all diagnostic modes disabled
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 192 13.1 using the internal fdl transmitter upon reset of the equad, the xfdl should be disabled by setting the en bit in the xfdl configuration register to logic 0. if data is not ready to be transmitted, the tdlint[x] output should also be masked by setting the inte bit to logic 0. when using the internal hdlc transmitter, the xfdl configuration register should be initialized for transmission: if the fcs is desired, the crc bit should be set to logic 1; if the block is to be used in interrupt driven mode, interrupts should be enabled by setting the inte bit to logic 1. finally, the xfdl can be enabled by setting the en bit to logic 1. if no message is sent after the en bit is set to logic 1, continuous flags will be sent. the xfdl can be used in a polled, interrupt driven, or dma-controlled mode for the transfer of frame data. in the polled mode, the tdlint[x] and tdludr[x] outputs of the xfdl are not used, and the processor controlling the xfdl must periodically read the xfdl status register to determine when to write to the xfdl transmit data register. in the interrupt driven mode, the processor controlling the xfdl uses either the tdlint[x] output, or the main processor intb output and the interrupt source registers, to determine when to write to the xfdl transmit data register. in the dma controlled mode, the tdlint[x] output of the xfdl is used as a dma request input to the dma controller, and the tdludr[x] output is used as an interrupt to the processor to allow handling of exceptions. the tdludr[x] output can also be enabled to generate a processor interrupt through the common intb output via the tdludre bit in the datalink options register. polled mode if the xfdl data transfer is operating in the polled mode (txdmasig, tfrace1, tdlinte, and tdludre bits in the datalink options register are set to logic 0), then a timer periodically starts up a service routine, which should process data as follows: 1. read the xfdl interrupt status register and poll the udr and int bits. 2. if udr=1, then clear the udr bit in the xfdl interrupt status register to logic 0, and restart the current frame. go to step 1. 3. if int=1, then: a) if there is still data to send, then write the next data byte to the xfdl transmit data register;
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 193 b) if all bytes in the frame have been sent, then set the eom bit in the xfdl configuration register to logic 1. 4. if eom bit was set to logic 1 in step 3b, then: a) read the xfdl interrupt status register and check the udr bit. b) if udr=1 then reset the udr bit in the xfdl interrupt status register and the eom bit in the xfdl configuration register to logic 0, and retransmit the last frame. 5. go to step 1. interrupt mode in the case of interrupt driven data transfer, the tdlint[x] output is connected to the interrupt input of the processor, and the interrupt service routine should process the data exactly as described above for the polled mode. the inte bit in the xfdl configuration register must be set to logic 1. alternately, the intb output can be connected to the interrupt input of the processor if the tdlinte bit of the datalink options register is set to logic 1. if this mode is used, additional polling of the interrupt id/clock monitor and master interrupt source registers must be performed to identify the cause of the interrupt before the initiating the interrupt service routine. dma-controlled mode the xfdl can also be used with a dma controller to process the frame data. in this case, the tdludr[x] output is connected to the processor interrupt input. the tdlint[x] output of the xfdl is connected to the dma request input of the dma controller. the inte bit in the xfdl configuration register must be set to logic 1 before enabling the xfdl. the dma controller writes a data byte to the xfdl whenever the tdlint[x] output is high. if there is a problem during transmission and an underrun condition occurs, then the tdludr[x] output goes high and the processor is interrupted. the processor can then halt the dma controller, reset the udr bit in the xfdl interrupt status register, reset the frame data pointers, and restart the dma controller to resend the data frame. after the message transmission is completed, the dma controller must initiate a write to set the eom bit in the xfdl configuration register and then verify that tdludr[x] is not set prior to setting eom.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 194 13.2 using the internal fdl receiver on power up of the equad, the rfdl should be disabled by setting the en bit in the configuration register to logic 0. the rfdl interrupt control/status register should then be initialized to select the fifo buffer fill level at which an interrupt will be generated. after the interrupt control/status register has been written to, the rfdl can be enabled at any time by setting the en bit in the configuration register to logic 1. when the rfdl is enabled, it will assume that the link status is idle (all ones) and immediately begin searching for flags. when the first flag is found, an interrupt will be generated (if enabled), and the byte received before the first flag was detected will be written into the fifo buffer. because the flg and eom bits are passed through the buffer, this dummy write allows the rfdl status register to accurately reflect the current state of the data link. a rfdl status register read after a rfdl data register read of the dummy byte will return eom as logic 1 and flg as logic 1. the first interrupt and data byte read after the rfdl is enabled (or tr bit set to logic 1) is an indication of the link status, and the data byte should therefore be discarded. it is up to the controlling processor to keep track of the link state as idle (all ones or bit-oriented messages active) or active (flags received). the rfdl can be used in a polled, interrupt driven, or dma controlled mode for the transfer of frame data. polled mode in the polled mode, the rdlint[x] and rdleom[x] outputs of the rfdl are not used, and the processor controlling the rfdl must periodically read the rfdl interrupt/status to determine when to read the data register. if the rfdl data transfer is operating in the polled mode, entry to the service routine is from a timer. the processor service routine should process the data in the following order: 1. poll the int bit in the rfdl interrupt/status register until it is set to logic 1. once int is set to logic 1, then proceed to step 2. 2. read the rfdl data register. 3. read the rfdl status register to check for the following: a) if ovr=1, then discard the current frame and go to step 1. else
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 195 b) if flg=0 (i.e. an abort has been received) and the link state was active, then set the link state to inactive, discard the current frame, and go to step 1. c) if flg=1 and the link state was inactive, then set the link state to active, discard the last data byte, and go to step 1. else d) save the last data byte read. e) if eom=1, then read the crc and nvb[2:0] bits of the rfdl status register to process the frame properly. f) if fe=0, then go to step 2, else go to step 1. the link state is typically a local software variable. the link state is inactive if the rfdl is receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. the link state is active if the rfdl is receiving flags or data. interrupt mode in the interrupt driven mode, the processor controlling the rfdl uses either the rdlint[x] output, or the main processor intb output (rdlinte bit of the datalink options register is set to logic 1), the interrupt id/clock monitor, and the interrupt source registers, to determine when to read the data register. the rxdmasig bit in the datalink options register should be set to logic 1. rdlinte of the same register should be set to logic 1 if the intb output is used as the interrupt source. the processor interrupt service routine should process the data in the following order: 1. wait for an interrupt originating from the rfdl. once the interrupt is set, then proceed to step 2. 2. read the rfdl data register. 3. read the rfdl status register to check for the following: a) if ovr=1, then discard the current frame and go to step 1. else b) if flg=0 (i.e. an abort has been received) and the link state was active, then set the link state to inactive, discard the current frame, and go to step 1.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 196 c) if flg=1 and the link state was inactive, then set the link state to active, discard the last data byte, and go to step 1. else d) save the last data byte read. e) if eom=1, then read the crc and nvb[2:0] bits of the rfdl status register to process the frame properly. f) if fe=0, then go to step 2, else go to step 1. dma-controlled mode the rfdl can also be used with a dma controller to process the frame data. in the dma controlled mode, the rdlint[x] output of the rfdl is used as a dma request input to the dma controller, and the rdleom[x] output is used as an interrupt to the processor to allow handling of exceptions and as an indication of when to process a frame. the rxdmasig bit of the datalink options register should be set to logic 1. the rdlint[x] output of the rfdl is connected through a gate to the dma request input of the dma controller to optionally inhibit the dma request if the rdleom[x] output is high. the dma controller reads the data bytes from the rfdl whenever the rdlint[x] output is high. when the current byte read from the data register is the last byte in a frame (due to an end-of-message or an abort), or an overrun condition occurs, then the rdleom[x] output goes high. the dma controller is inhibited from reading any more bytes, and the processor is interrupted. the processor can then halt the dma controller, read the status register, process the frame, and finally reset the dma controller to process the data for the next frame. the rdleom[x] output can optionally be enabled to generate a processor interrupt through the common intb output via the rdleome bit in the datalink options register, rather than tying the rdleom[x] output directly to the microprocessor. this allows a central microprocessor controlling the equad operation to also respond to conditions affecting the dma servicing of rfdl. when using the intb output, the central processor must poll the interrupt id/clock monitor, and the interrupt source registers to identify the source of the interrupt before beginning any interrupt service routine.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 197 figure 23 - typical data frame transmit 87654321 01111110 flag address (high) (low) control frame check sequence (fcs) 01111110 flag bit: data bytes received and transferred to the fifo, bit 1 first data bytes written to the transmit data register and serially transmitted, bit 1 first appended after eom is set, if crc is set receive bit 1 is the first serial bit to be transmitted or received. both the address and control bytes must be supplied by an external processor and are shown for reference purposes only. key used on subsequent diagrams: flag - flag sequence (01111110) abort - abort sequence (01111111) d1 - dn - n frame data bytes r - remainder bits (less than 8) c1, c2 - crc-ccitt information b1, b2, b3 - groupings of 8 bits
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 198 figure 24 - rfdl normal data and abort sequence serial data extracted from esf fdl rdlint[x] rdleom[x] d[7:0] flag d1 d2 d3 dn rc1 c2 flag d1 b1 b2 b3 d1 dn-2 dn-1 dn b1 b2 b3 d2 dn-1 dn-3 d1 b1 abort eom eom b1 r abort this diagram shows the relationship between rfdl inputs and outputs for the case where interrupts are programmed to occur when one byte is present in the fifo buffer. the rfdl is assumed to be operating in the interrupt driven mode. each read shown is composed of two register reads: first a read of the rfdl data register, followed by a read of the rfdl status register. a read of the rfdl data register sets the rdlint[x] output to low if no more data exists in the fifo buffer. the status of the fe bit returned in the rfdl status register read will indicate the fifo buffer fill status as well. the rfdl data register read dn-2 is shown to occur after two bytes have been written into the buffer. the rdlint[x] output does not go low after the first rfdl data register read because a data byte still remains to be read. the rdlint[x] output goes low after rfdl data register read dn-1. the fe bit will be logic 0 in rfdl status register read dn-2 and logic 1 in rfdl status register read dn-1. the rdleom[x] output goes high as soon as the last byte in the frame is read from the rfdl data register. the rdlint[x] output will go low if the fifo buffer is empty. the next rfdl status register read will return a value of logic 1 for the eom and flg bits, and cause the rdleom[x] output of the rfdl to return low. in the next frame, the first data byte is received, and after a delay of ten bit periods, it is written to the fifo buffer, and read by the processor after the interrupt. when the abort sequence is detected, the data received up to the abort is written to the fifo buffer and an interrupt generated. the processor then reads the partial byte from the rfdl data register and the rdleom[x] output is set high. the processor then reads the rfdl status register which will return a value of logic 1 for the eom and flg bits, and set the rdleom[x]
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 199 output low. the fifo buffer is not cleared when an abort is detected. all bytes received up to the abort are available to be read. after an abort, the rfdl state machine will be in the receiving all ones state, and the data link status will be idle. when the first flag is detected, a new interrupt will be generated, with a dummy data byte loaded into the fifo buffer, to indicate that the data link is now active. figure 25 - rfdl fifo overrun serial data extracted from esf fdl rdlint[x] rdleom[x] d[7:0] flag d1 d2 d3 dn r c1 c2 flag d1 b1 b2 b3 d1 statusrd d2 dn-1 ovr r abort this diagram shows the relationship between rfdl inputs and outputs for the case where interrupts are programmed to occur when two data bytes are present in the fifo buffer. each read is composed of two register reads, as described above. in this example, data is not read by the end of b2. an overrun occurs since unread data (dn-3) has been overwritten by b1. this sets the rdleom[x] output high, and resets both the rfdl and the fifo buffer. the rfdl is held disabled until the rfdl status register is read. the start flag sequence is not detected since the rfdl is still held disabled when it occurs. consequently, the rfdl will ignore the entire frame including the abort sequence (since it has not occurred in a valid frame or during flag reception, according to the rfdl).
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 200 figure 26 - xfdl normal data sequence flag d1 d2 dn crc1 crc2 flag d1 d1 d2 d3 d4 d2 d3 tdlint[x] d[7:0] inte eom d1 inte inte serial data inserted into esf fdl this diagram shows the relationship between xfdl inputs and outputs for the case where interrupts and crc are enabled for regular data transmission. the process is started by setting the inte bit in the xfdl configuration register to logic 1, thus enabling the tdlint[x] signal. when tdlint[x] goes high, the interrupt service routine is started, which writes the first byte (d1) of the data frame to the xfdl transmit data register. when this byte begins to be shifted out on the data link, tdlint[x] goes high. this restarts the interrupt service routine, and the next data byte (d2) is written to the xfdl transmit data register. when d2 begins to be shifted out on the data link, tdlint[x] goes high again. this cycle continues until the last data byte (dn) of the frame is written to the xfdl transmit data register. when dn begins to be shifted out on the data link, tdlint[x] again goes high. since all the data has been sent, the interrupt service routine sets the eom bit in the xfdl configuration register to logic 1. the tdlint[x] interrupt should also be disabled at this time by setting the inte bit in the xfdl configuration register to logic 0. the xfdl will then shift out the two-byte crc word and closing flag, which ends the frame. whenever new data is ready, the tdlint[x] signal can be re-enabled by setting the inte bit in the xfdl configuration register to logic 1, and the cycle starts again.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 201 figure 27 - xfdl underrun sequence flag d1 d2 flag d2 tdlint[x] d3 d1 d2 d3 tdludr[x] d3 abort d1 udr d4 d1 d2 d[7:0] inte inte inte serial data inserted into esf fdl this diagram shows the relationship between xfdl inputs and outputs in the case of an underrun error. an underrun error occurs if the xfdl finishes transmitting the current message byte before the processor writes the next byte into the xfdl transmit data register; that is, the processor fails to write data to the xfdl in time. in this example, data is not written to the xfdl within the time-out period after tdlint[x] goes high at the beginning of the transmission of byte d3. the tdludr[x] interrupt becomes active at this point, and an abort, followed by a flag, is sent out on the data link. meanwhile, the processor must clear the tdludr[x] interrupt by setting the udr bit in the xfdl interrupt status register to logic 0. the tdlint[x] interrupt should also be disabled at this time by setting the inte bit in the xfdl configuration register to logic 0. the data frame can then be restarted as usual, by setting the inte bit logic to 1. transmission of the frame then proceeds normally. 13.3 using the loopback modes the equad provides three loopback modes to aid in network and system diagnostics. the network loopbacks (payload and line) can be initiated at any time via the microprocessor interface, but are usually initiated once an inband loopback activate code is detected. the system loopback (diagnostic) can be initiated at any time by the system via the microprocessor interface to check the path of system data through the transceiver.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 202 13.3.1 payload loopback when payload loopback (paylb) is initiated by writing 20h to the master diagnostics register (00ah) and disabling the tpsc by clearing the pcce bit in the tpsc configuration register (030h) to 0, the framer is configured to internally connect the output of the elst to the pcm input of tran. payload loopback will only function if there is a valid btclk input signal and a valid btfp signal (alternatively, btfp can be tied either high or low). btfp cannot, though, be derived from the brfpo output of the loopbacked channel. the data is read out of elst timed to the transmitter clock, and the transmit frame alignment indication is used to synchronize the output frame alignment of elst. note that the btsig[x] stream is still presented to the tran; therefore, the sigen and dlen bits of the tran configuration register should be cleared to logic 0 if the signaling is to be looped back. the btsig[x], btclk[x] and btfp[x] signals must be active during payload loopback. conceptually, the data flow through a single e1 framer in this loopback condition can be shown as follows: figure 28 - payload loopback network dtif djat tran cdrc frmr elst btsig[x] btpcm[x] btclk[x] brfpi brclk btfp[x] brpcm[x] ais system rdp/rdd[x] rclki[x] rdn/rlcv[x] tdp/tdd[x] tclko[x] tdn/tflg[x]
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 203 13.3.2 line loopback when line loopback (linelb) is initiated by writing 10h to the master diagnostics register, the framer is configured to internally connect the dual-rail positive and negative line data pulses output from cdrc to the dual-rail inputs of djat. if either the transmit or receive is in unipolar mode, the appropriate line decoding or encoding is performed. conceptually, the data flow through a single framer in this loopback condition can be shown as follows: figure 29 - line loopback dtif djat tran cdrc frmr elst btsig[x] btpcm[x] btclk[x] brfpi brclk btfp[x] brpcm[x] system rpcm rclk rp rn network rdp/rdd[x] rclki[x] rdn/rlcv[x] tdp/tdd[x] tclko[x] tdn/tflg[x] 13.3.3 diagnostic digital loopback when diagnostic digital loopback (ddlb) is initiated by writing 04h to the master diagnostics register, the framer is configured to internally connect the data and clock outputs from the djat to the cdrc. when the framer is configured for dual-rail operation (runi=0, tuni=0), the dual-rail positive and negative data pulses output from djat are connected to the dual-rail inputs of cdrc. clock recovery can be enabled or disabled in the cdrc and diagnostic digital loopback will also operate when the framer is configured for single-rail operation (runi=1, tuni=1).
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 204 conceptually, the data flow through a single framer in this loopback condition can be shown as follows: figure 30 - diagnostic digital loopback djat tran frmr elst btsig[x] btpcm[x] btclk[x] brfpi brclk btfp[x] brpcm[x] system rpcm rclk dtif optional ais network cdrc rdp/rdd[x] rclki[x] rdn/rlcv[x] tdp/tdd[x] tclko[x] tdn/tflg[x] 13.4 using the per-channel serial controllers 13.4.1 initialization before the tpsc block can be used, a proper initialization of the internal registers must be performed to eliminate erroneous control data from being produced on the block outputs. the output control streams should be disabled by setting the pcce bit in the tpsc configuration register to logic 0. then, all 64 locations of the tpsc must be filled with valid data. finally, the output streams can be enabled by setting the pcce bit in the tpsc configuration register to logic 1.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 205 13.4.2 direct access mode direct access mode to the tpsc is not used in the equad. however, direct access mode is selected by default whenever the equad is reset. the ind bit within the tpsc configuration register must be set to logic 1 after a reset is applied. 13.4.3 indirect access mode indirect access mode is selected by setting the ind bit in the tpsc configuration register to logic 1. when using the indirect access mode, the status of the busy indication bit should be polled to determine the status of the microprocessor access: when the busy bit is logic 1, the tpsc is processing an access request; when the busy bit is logic 0, the tpsc has completed the request. the indirect write programming sequence for the tpsc is as follows: 1. check that the busy bit in the tpsc p access status register is logic 0. 2. write the timeslot data to the tpsc timeslot indirect data buffer register. 3. write rwb=0 and the timeslot address to the tpsc timeslot indirect address/control register. 4. poll the busy bit until it goes to logic 0. the busy bit will go to logic 1 immediately after step 3 and remain at logic 1 until the request is complete. 5. if there is more data to be written, go back to step 1. the indirect read programming sequence for the tpsc is as follows: 1. check that the busy bit in the tpsc p access status register is logic 0. 2. write rwb=1 and the timeslot address to the tpsc timeslot indirect address/control register. 3. poll the busy bit, waiting until it goes to a logic 0. the busy bit will go to logic 1 immediately after step 2 and remain at logic 1 until the request is complete. 4. read the requested timeslot data from the tpsc timeslot indirect data buffer register.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 206 5. if there is more data to be read, go back to step 1. 13.5 using the digital jitter attenuator the key to using djat lies in selecting the appropriate divisors for the phase comparison between the selected reference clock and the generated smooth tclko. 13.5.1 default application upon reset, the equad default condition provides jitter attenuation with tclko[x] referenced to the transmit clock, btclk[x]. the djat sync bit is also logic 1 by default. djat is configured to divide its input clock rate, btclk[x], and its output clock rate, tclko[x], both by 48, which is the maximum length of the fifo. these divided down clock rates are then used by the phase comparator to update the djat dpll. the phase delay between btclk[x] and tclko[x] is synchronized to the physical data delay through the fifo. for example, if the phase delay between btclk[x] and tclko[x] is 12ui, the fifo will be forced to lag its output data 12 bits from its input data. the default mode works well with the transmit backplane running at 2.048mhz. 13.5.2 data burst application in applications where a higher transmit backplane rate with external gapping is used, a few factors must be considered to adequately filter the resultant tclko[x] into a smooth 2.048mhz clock. the magnitude of the phase shifts in the incoming bursty data can be too large to be properly attenuated by the pll alone. however, the magnitudes, and the frequency components of these phase shifts are known, and are most often multiples of 8 khz. when using a gapped higher rate clock, the phase shifts of the input clock with respect to the generated tclko[x] in this case can be large, but when viewed over a longer period, such as a frame, there is little net phase shift. therefore, by choosing the divisors appropriately, the large phase shifts can be filtered out, leaving a stable reference for the dpll to lock onto. in this application, the n1 and n2 divisors should be changed to ffh (i.e. divisors of 256). consequently, the frequency of the clock inputs to the phase discriminator in the pll is 8 khz. the djat sync option must be disabled, since the divisor magnitude of 256 is not an integer multiple of the fifo length, 48. the self-centering circuitry of the fifo should be enabled by setting the cent register bit. this sets up the fifo read pointer to be at least 4 ui away from the
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 207 end of the fifo registers, and then disengages. should variations in the frequency of input clock or the output clock cause the read pointer to drift to within one unit interval of fifo overflow or underflow, the pointer will be incrementally pushed away by the limit control without any loss of data. with sync disabled, cent and limit enabled, the maximum tolerable phase difference between the bursty input clock and the smooth tclko is 40ui. phase wander between the two clock signals is compensated for by the limit control. 13.5.3 elastic store application in multiplex applications where the jitter attenuation is not required, the djat fifo can be used to provide an elastic store function. for example, in a m12 application, the data is written into the fifo at 2.048mhz and the data is read out of the fifo with a gapped e2 rate clock applied on tclki[x]. in this configuration, the timing options oclksel[1:0] bits should be programmed to 01, the tclkisel bit should be programmed to 1, and the smclko bit should be programmed to 1. also, the djat sync and limit bits should be disabled and the cent bit enabled. this provides the maximum phase difference between the input clock and the gapped output clock of 40ui. the maximum jitter and wander between the two clocks is 8uipp. 13.5.4 alternate tclko reference application in applications where tclko[x] is referenced to an nx8 khz clock source applied on tclki[x], djat can be configured by programming the output clock divisor, n2, to ffh and the input clock divisor, n1, to the value (n-1). the resultant input clocks to the phase comparator are both 8khz. the djat sync and limit bits should be disabled in this configuration.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 208 13.5.5 changing the jitter transfer function the djat phase lock loop has a single order low pass jitter transfer function. by default, the corner frequency is 8.8 hz. the corner may be moved by the appropriate selection of clock divisors: f c = 2048 khz where f c = corner frequency 1536 p (n2+1) n2 = value in the output clock divisor control register ensure the reference clock divisor control value (n1) is also modified to satisfy: f ref = 2048 khz n1+1 n2+1 13.5.6 receiver jitter attenuation the combination of the receive elastic store and the digital phase locked loop may be used to attenuate jitter in the receive direction by locking the elastic store output clock to the recovered clock. the following diagram illustrates the concept. fig. 30 timing options for receiver jitter attenuation recovered clock 11 elst elst input data clock djat pll 01 10 pllref[1:0] 00 rclko[x] 0 1 smclko smooth 2.048mhz "jitter-free" 2.048mhz elst output data clock 1 0 brclk rclkosel 1 0
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 209 the jitter on the recovered clock is absorbed by the two frame slip buffer in the elastic store. brpcm[x], brsig[x], and brfpo[x] are updated on the falling edge of rclko[x]. the framing alignment on brpcm[x] and brsig[x] is still set by the brfpi input. however, brfpi must now be timed with respect to the individual output clock rclko[x] instead of brclk for each quadrant of the equad in which rclkosel is set to logic 1. a possible configuration would have rclkosel set to logic 1 in only one quadrant and brfpi timed to that quadrant's rclko. the same rclko can then be connected to brclk which will be used as the timing reference for all the other quadrants which will have rclkosel set to logic 0. otherwise, if backplane frame alignment is not necessary, rclkosel can be set to logic 1 in every quadrant and brfpi should be tied low. figure 31 shows the functional waveforms for a configuration where rclkosel is set to logic 1 in quadrant x. brfpi and all the backplane outputs are timed to rclko[x]. figure 31 - receive backplane interface with rclkosel = 1 1 2345678 abcd 1 2345678 1 2345678 abcd 1 2345678 1 2345678 abcd timeslot 31 timeslot 0 timeslot 1 timeslot 16 timeslot 17 rclko[x] brfpo[x] brpcm[x] brsig[x] brfpi undefined undefined undefined it should also be noted that rfp[x] can no longer be sampled by rclko[x] since rclko[x] is a smoothed version of the recovered clock, and rfp[x] is timed by the unsmoothed recovered clock. register bits trslip and elstbyp in the receive options register and brx2rail in the receive backplane options register must be cleared to logic 0 for proper operation. the djat configuration register should be cleared to all zeros to disable the limit and sync bits. note that the djat pll is no longer in the transmit path. therefore, the fifobyp bit of the transmit interface configuration register must be set. to logic 1.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 210 13.6 using the performance monitor counter values all pmon block event counters are of sufficient length so that the probability of counter saturation over a one second interval at a 10 -3 ber is less than 0.001%. the odds of any one of the counters saturating during a one second sampling interval go up as the ber increases. at some point, the probability of counter saturation reaches 50%. this point varies, depending upon the framing format and the type of event being counted. the ber at which the probability of counter saturation reaches 50% is shown below for various counters: ta bl e 7 - counter ber lcv 4.0 x 10 -3 fer 4.0 x 10 -3 crce cannot saturate febe cannot saturate below these 50% points, the relationship between the ber and the counter event count (averaged over many one second samples) is essentially linear. above the 50% point, the relationship between ber and the average counter event count is highly non-linear due to the likelihood of counter saturation. figure 32-figure 34 show this relationship for various counters and framing formats. these graphs can be used to determine the ber, given the average event count. in general, if the ber is above 10 -3 , the average counter event count cannot be used to determine the ber without considering the statistical effect of occasional counter saturation.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 211 figure 32 - lcv count vs. ber 10000 4000 2000 0 6000 8000 line code violation count per second 0 1 2 3 4 5 bit error rate (x 10 ) -3 average count over many 1 second intervals figure 33 - fer count vs. ber 0 50 100 150 200 250 0 1 2 3 4 5 6 7 8 9 average count over many 1 second intervals bit error rate (x 10 ) -3 framing bit error count per second since the maximum number of crc sub-multiframes that can occur in one second is 1000, the 10-bit febe and crce counters cannot saturate in one second. despite this, there is not a linear relationship between ber and crc-4 block errors due to the nature of the crc-4 calculation. at bers below 10 -4 , there tends to be no more than one bit error per sub-multiframe, so the number of crc-4 errors is generally equal to the number of bit errors, which is directly related to the ber. however, at bers above 10 -4 , each crc-4 error is often due to more than one bit error. thus, the relationship between ber and crce
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 212 count becomes non-linear above a 10 -4 ber. this must be taken into account when using crc-4 counts to determine the ber. since febes are indications of crces at the far end, and are accumulated identically to crces, the same explanation holds for the febe event counter. figure 34 - crce count vs. ber 0 1000 200 400 600 800 1200 0 4 8 12 16 20 average count over many 1 second intervals crc error event count per second bit error rate (x 10 ) -4 13.7 reset procedure in the sigx block that there is a small state machine which will not clear itself out if it happens to get in an all-ones state. the result is that the sigx remains frozen after a reset. the probability that this state will occur is very small, about 1 in 3600 or about 0.028 percent probability of occurrence. if the sigx function is not being used, then this condition is a don't care. to prevent this state from occurring hold the brclk and the btclk[4:1] signals low for at least 65ns (greater than one cycle of an 8x clock) after a hardware or software reset. if elstbyp is to be set, do not do so within 65ns of a hardware or software reset. for designs where it is not possible to implement the above hardware solution, the software solution is to perform a self-test after every reset. this self-test routine would use the tpsc functional block to source known signaling data, which would be looped back to the sigx. if the sigx can detect changes in the signaling data, then the sigx block is okay; if it cannot detect changes in the signaling data, then a reset must be performed and the self-test repeated (until the sigx is okay).
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 213 here are the suggested steps to be taken after every reset (software or hardware reset) of an equad in which the sigx functional block is being used. this procedure should be performed on each quadrant in the equad. 1) initialize all indirect registers (including ts0 and ts16). the data control registers contained in pcsc for ts0 and ts16 should not be written to. 2) perform the reset (software or hardware). a software reset is performed by setting then clearing the reset bit in register 00dh, 08dh, 10dh or 18dh (depending on the quadrant). a hardware reset is performed by asserting the rstb pin low, then deasserting high. the reset will make all the equad's normal mode registers revert to their default state as described in the equad databook section entitled "register description." this default state enables the equad to operate as described in the equad databook section entitled "configuring the equad from reset." note that indirect registers contained in the sigx and pcsc are not affected by a reset. 3) configure and enable the pcsc functional block for the self-test. the method of accessing the indirect registers within the pcsc functional block is explained in the equad databook section entitled "using the per- channel serial controllers." the pcsc should be configured as follows: a) set the ind bit in quadrant 1 register 030h (0b0h, 130h or 1b0h for quadrants 2, 3 and 4) to a logic one. this will enable access to the pcsc indirect registers. b) program the pcsc indirect registers such that, for all channels, the data control byte is equal to f5h. the idle code bytes can be left (they are don't-cares). this will configure the pcsc to insert -law digital milliwatt patterns into all channels, and to insert a signaling state of abcd=0101. c) set the pcce bit in quadrant 1 register 030h (0b0h, 130h, 1b0h for quadrants 2, 3 and 4) to a logic one. this will enable the pcsc to perform the functions configured in step (b) above. 4) configure the sigx functional block for the self-test.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 214 the method of accessing the indirect registers within the sigx functional block is the same as that explained in the equad databook section entitled "using the per-channel serial controllers." the sigx should be configured as follows: a) set the ind bit in quadrant 1 register 040h (0c0h, 140h or 1c0h for quadrants 2, 3 or 4) to a logic one. this will enable accesses to the sigx indirect registers. b) program the sigx indirect registers such that, for timeslots 1-15 and 17- 31 the per-timeslot configuration and signaling trunk conditioning data registers contain 10h. this will configure the sigx to debounce the received signaling states as explained in the rdebe bit description. c) set the pcce bit in register 040h (0c0h, 140h, 1c0h) to a logic one. this will enable the sigx to perform the functions configured in step (b) above. 5) configure for diagnostic digital loopback. to accomplish this: a) program quadrant 1 register 00ah (08ah, 10ah or 18ah for quadrants 2, 3 or 4) to 04h. this will enable the diagnostic digital loopback mode of the equad which internally loops back the transmit data to the receive circuitry. this mode is sometimes called a "local" loopback. b) program register 10h (090h, 110h, 190h) to default value of 00h and register 44h (0c4h, 144h, 1c4h) to 70h for crc generation. program register 20h to 80h to enable crc framing. this will enable the receiver to accept the hdb3-encoded signal sourced by the transmitter. 6) disable elastic store. this can be done by bypassing elastic store. to do this, program register 00h (080h, 100h, 180h) to a value of 20h. 7) wait until the frmr functional block is solidly in-frame. this can be determined by polling the oof, oosmf and oocmf bits in register 026h (0a6h, 126h, 1a6h) and the oofi, oosmfi and oocmfi bits in register 024h (0a4h, 124h, 1a4h). when the oof, oosmf and oocmf bits are low (logic zero) for two consecutive polls, and the oofi, oosmfi and oocmfi bits are low (logic zero) on the second consecutive poll, then you can assume that the frmr functional block of the current quadrant of the equad has found a stable frame alignment pattern.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 215 8) further wait until at least five signaling multiframes have been received (> 10 ms) to give sigx time to unfreeze and debounce the signaling data. 9) verify that the sigx signaling data registers contain the expected value (that transmitted by the pcsc functional block). if not, return to step (1). this is accomplished by reading the sigx typical timeslot signaling for timeslots 1- 15 and 17-31. the values returned should contain 55h -- if not, return to step (1). 10)change the signaling data transmitted by the pcsc for all channels. a value of ffh should be written to the pcsc data control byte for timeslots 1-15 and 17-31. this will configure the pcsc to insert a signaling state of abcd=1111. 11) wait until at least three signaling multiframes have been received (> 6 ms) to give sigx time to extract and debounce the new signaling data. 12) verify that the sigx signaling data registers contain the new values. if not, return to step (1). this is accomplished by reading the sigx typical timeslot signaling data registers for timeslots 1-15, 17-31. the values returned should contain ffh. if not, return to step (1). 13) the self-test passed -- the equad is ready for operation. the equad can now be configured for the desired application. it is allowable to reconfigure the pcsc and sigx functional blocks. every time a reset (software or hardware) occurs, the above procedure, steps (1) through (13), should be performed for each quadrant in the equad.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 216 14 absolute maximum ratings ambient temperature under bias -55c to +125c storage temperature -65c to +150c voltage on vdd with respect to gnd -0.5v to +7.0v voltage on any pin vss-0.5v to vdd+0.5v static discharge voltage 1000 v
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 217 15 capacitance table 8 - equad capacitance symbol parameter typical units conditions cin input capacitance 5 pf t a = 25c, f = 1 mhz cout output capacitance 5pft a = 25c, f = 1 mhz cbidir bidirectional capacitance 5pft a = 25c, f = 1 mhz
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 218 16 d.c. characteristics ta= -40 to +85c, vdd=5v 10% table 9 - equad d.c. characteristics symbol parameter min typ max units conditions pha, phd power supply 4.5 5 5.5 volts v il input low voltage -0.5 0.8 volts guaranteed input low voltage v ih input high voltage 2.0 v dd +0 .5 volts guaranteed input high voltage v ol output or bidirectional low voltage 0.1 0.4 volts v dd = min, i ol = -4 ma for d[7:0] and mrd and -2 ma for others 3 v oh output or bidirectional high voltage v dd - 1.0 4.5 volts v dd = min, i ol = 4 ma for d[7:0] and mrd and 2 ma for others 3 v t+ reset input high voltage 3.5 volts v t- reset input low voltage 0.6 volts v th reset input hysteresis voltage 1.4 volts i ilpu input low current 1,3 +100 +350 +525 a v il = gnd
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 219 symbol parameter min typ max units conditions i ihpu input high current 1,3 -10 0 +10 a v ih = v dd i il input low current 2,3 -10 0 +10 a v il = gnd i ih input high current 2,3 -10 0 +10 a v ih = v dd i ddop operating current 47 80 ma v dd = 5.5 v, outputs unloaded, xclk = 49.152 mhz btclk[4:1] = 2.048mhz notes on d.c. characteristics: 1. input pin or bidirectional pin with internal pull-up resistors. 2. input pin or bidirectional pin without internal pull-up resistors 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 220 17 microprocessor interface timing characteristics ta= -40 to +85c, vdd=5v 10% table 10 - microprocessor read access (figure 35) symbol parameter min max units ts ar address to valid read set-up time 10 ns th ar address to valid read hold time 5 ns ts alr address to latch set-up time 10 ns th alr address to latch hold time 10 ns tv l valid latch pulse width 20 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns tp rd valid read to valid data propagation delay 80 ns tz rd valid read negated to output tri-state 20 ns tz inth valid read negated to intb high 50 ns
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 221 figure 35 - microprocessor read access timing intb tz inth (csb+rdb) valid data d[7:0] tp rd tz rd ts ar th ar valid address a[9:0] ale ts alr tv l ts lr th alr th lr notes on microprocessor read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 50 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 222 4. microprocessor interface timing applies to normal mode register accesses only. 5. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 6. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 7. in non-multiplexed address/data bus architectures ale should be held high and parameters ts alr , th alr , tv l , ts lr and th lr are not applicable. 8. parameter th ar is not applicable when address latching is used. 9. output tristate delay is the time in nanoseconds from the 1.4 volt point of the reference signal to 300mv of the termination voltage on the output. the test load is 50 w to 1.4v in parallel with 10 pf to gnd. table 11 - microprocessor write access (figure 36) symbol parameter min max units ts aw address to valid write set-up time 10 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 10 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 20 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 223 figure 36 - microprocessor write access timing th dw valid data d[7:0] tv wr ts aw th aw ts dw (csb+wrb) a[9:0] valid address ale tv l ts alw ts lw th alw th lw notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. microprocessor interface timing applies to normal mode register accesses only. 3. in non-multiplexed address/data bus architectures, ale should be held high and parameters ts alw , th alw , tv l , ts lw and th lw are not applicable. 4. parameters th aw and ts aw are not applicable if address latching is used. 5. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 224 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 225 18 equad i/o timing characteristics ta= -40 to +85c, vdd=5v 10% table 12 - backplane transmit input timing, menb input high (figure 37) symbol description min max units f btclk backplane transmit clock frequency 1,2 (typically 2.048 mhz 50 ppm) 2.1 mhz td btclk backplane transmit clock duty cycle 30 70 % ts tclk btclk[x] to backplane input set-up time 7 20 ns th tclk btclk[x] to backplane input hold time 8 20 ns figure 37 - backplane transmit input timing diagram btclk[x] valid t stclk t htclk btpcm/btdp[x], btsig/btdn[x], btfp[x]
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 226 table 13 - backplane transmit input timing, menb input low (figure 37) symbol description min max units t mtclk backplane transmit clock frequency 2,3 (typically 16.384 mhz 50 ppm) 16.8 mhz td mtclk backplane transmit clock duty cycle 40 60 % ts mtclk mtclk to backplane input set- up time 7 10 ns th mtclk mtclk to backplane input hold time 8 3ns figure 38 - backplane transmit input timing diagram mtd, mtfp mtclk valid t smtclk t hmtclk
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 227 table 14 - xclk=49.152 mhz input (figure 39) symbol description min max units t l xclk xclk low pulse width 4 8ns t h xclk xclk high pulse width 4 8ns t xclk xclk period (typically 1/49.152 mhz) 5 20 ns figure 39 - xclk=37.056 mhz input timing xclk t l t h t xclk xclk xclk table 15 - tclki input (figure 40 symbol description min max units f1 tclki tclki[x] frequency (when used for djat ref or for mux operation), typically 2.048 mhz 50 ppm 2,6 2.10 mhz f2 tclki tclki[x] frequency (when djat pll not used), typically 16.384 mhz 16.8 mhz t h tclki tclki[x] high duration 6 100 ns t l tclki tclki[x] low duration 6 100 ns
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 228 figure 40 - tclki input timing tclki[x] t l tclki t h tclki t tclki table 16 - digital receive interface input timing (figure 41) symbol description min max units f rclki digital receive clock rclki[x] frequency (nominally 2.048 mhz 50 ppm) 2 2.1 mhz tlo rclki rclki[x] low duration 145 2 ns thi rclki rclki[x] high duration 145 2 ns ts rclki rclki[x] to nrz receive input set-up time 7 20 ns th rclki rclki[x] to nrz receive input hold time 8 20 ns tw rdpn rz receive input pulse width 2,4 200 300 ns
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 229 figure 41 - digital receive interface input timing diagram rclki[x] tlo rclki rclki thi rdp/rdd[x], rdn/rlcv[x] rclki[x] valid rclki rclki with rfall bit =1, dcr or runi=1 rdp/rdd[x], rdn/rlcv[x] rclki[x] valid with rfall bit =0, dcr or runi=1 rdp[x], rdn[x] rdpn with dcr=0 & runi=0 t s t h rclki t s rclki t h t w
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 230 table 17 - transmit data link input timing (figure 42) symbol description min max units ts din tdlclk[x] to tdlsig[x] input set-up time 7 80 ns th din tdlclk[x] to tdlsig[x] input hold time 8 20 ns figure 42 - transmit data link input timing diagram tdlclk sdin t hdin t tdlsig
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 231 table 18 - backplane receive timing, menb input high (figure 43) symbol description min max units t s brfpi brclk to brfpi input set-up time 7 20 ns t h brfpi brclk to brfpi input hold time 8 20 ns t p brclk brclk to backplane output signals propagation delay 9,10 50 ns f1 brclk brclk freq. - reg 07h hsbpsel=0 2 2.41 mhz f2 brclk brclk freq. - reg 07h hsbpsel=1 2 3.00 mhz figure 43 - backplane receive timing diagram valid t pbrclk brpcm/brdp[x], brsig/brdn[x], brfpo[x] brclk t sbrfpi t hbrfpi brfpi
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 232 table 19 - backplane receive timing, menb input high, rclkosel = 1 (figure 44) symbol description min max units t s brfpio rclko to brfpi input set-up time 7 25 ns t h brfpio rclko to brfpi input hold time 8 20 ns t p brclko rclko to backplane output signals propagation delay 9,10 50 ns figure 44 - backplane receive timing (rclkosel = 1) diagram valid t pbrclko brpcm/brdp[x], brsig/brdn[x], brfpo[x] rclko[x] t sbrfpio t hbrfpio brfpi
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 233 table 20 - multiplexed backplane receive timing, menb input low (figure 45) symbol description min max units t s mrfpi mrclk to mrfpi input set-up time 7 10 ns t h mrfpi mrclk to mrfpi input hold time 8 2ns t p mrd brclk to mrd propagation delay 9,10 25 ns figure 45 - multiplexed backplane receive timing diagram valid t pmrd mrd mrclk t smrfpi t hmrfpi mrfpi
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 234 table 21 - receive data link output timing (figure 46) symbol description min max units t p rdlclk rdlclk[x] to rdlsig[x] propagation delay 9,10 50 ns figure 46 - receive data link output timing diagram rdlclk[x] valid t prdlclk rdlsig[x] table 22 - recovered frame pulse output timing (figure 47) symbol description min max units t p rfp rclko[x] to recovered frame pulse (rfp[x]) propagation delay (rclkosel = 0) 9,10 50 ns figure 47 - recovered frame output timing diagram rclko[x] valid t prfp rfp[x]
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 235 table 23 - transmit interface output timing (figure 48) symbol description min max units t p tclko tclko[x] to digital transmit data output signals propagation delay 9,10 50 ns figure 48 - transmit interface output timing diagram tclko[x] valid t ptclko tdp/tdd[x], tdn/tflg[x] with trise bit=0 tclko[x] valid t ptclko tdp/tdd[x], tdn/tflg[x] with trise bit= 1
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 236 table 24 - transmit data link dma interface output timing (figure 49) symbol description min max units tp tint transmit data register serviced (wrb low) to tdlint[x] low propagation delay 9,10 50 ns tp tudr xfdl udr bit written low (wrb high) to tdludr[x] low propagation delay 9,10 50 ns figure 49 - transmit data link dma interface output timing diagram wrb tdlint[x] ptint t t ptudr tdludr[x]
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 237 table 25 - receive data link dma interface output timing (figure 50) symbol description min max units tp rint receive data register serviced (rdb low) to rdlint[x] low propagation delay 9,10 70 ns tp r1eom receive data register serviced (rdb low) to rdleom[x] high propagation delay 9,10 80 ns tp r2eom receive status register serviced (rdb high) to rdleom[x] low propagation delay 9,10 50 ns figure 50 - receive data link dma interface output timing diagram rdb rdlint[x] print t t pr1eom t pr2eom rdleom[x] notes on input timing: 1. btclk[x] can be a jittered clock signal subject to the minimum and maximum instantaneous frequencies and duty cycles shown.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 238 2. guaranteed by design for nominal xclk input frequencies (49.152 mhz 50 ppm or 16.384 mhz 50 ppm). 3. mtclk can be a jittered clock signal subject to the minimum and maximum instantaneous frequencies and duty cycles shown. these specifications correspond to nominal xclk input frequencies. 4. high pulse width is measured from the 1.4 volt points of the rise and fall ramps. low pulse width is measured from the 1.4 volt points of the fall and rise ramps. 5. xclk accuracy is 50 ppm. 6. tclki[x] can be a jittered clock signal subject to the minimum high and low durations th tclki , tl tclki . these durations correspond to nominal xclk input frequencies. 7. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 8. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. notes on output timing: 9. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 10. output propagation delays are specified with a 50 pf load.
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 239 19 ordering and thermal information table 26 - equad ordering information part no description pm6344-ri 128 plastic quad flat pack (pqfp) table 27 - equad thermal information part no. ambient temperature theta ja theta jc pm6344-ri -40c to 85c 50 c/w 16 c/w
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 240 20 mechanical information figure 51 - 128 pin copper leadframe plastic quad flat pack (r suffix) e 1 d e1 d1 e 128 8-12 deg a 8-12 deg a2 pin 1 designator nom. min. max. dim. aa1 a2 d d1 e e1 l e b ccc package type: body size: 14.10 14.00 13.90 0.73 0.88 1.03 0.10 14 x 20 x 2.7 mm 2.82 3.40 0.25 0.53 2.57 2.70 2.87 22.95 23.20 23.45 19.90 20.00 20.10 16.95 17.20 17.45 0.50 0.17 0.22 0.27 see detail a 128 pin metric rectangular plastic quad flatpack-mqfp gage plane, 0.25 above seating plane. detail a 0-7 deg plane seating 0.13-0.23 c l .25 a 0-10 deg. ccc c lead coplanarity notes: 1) all dimensions in millimeter. b standoff a1 3) foot length "l" is measured at c with tolerances as indicated. 2) dimensions shown are nominal
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 241 notes
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer 242 notes
standard product pmc-sierra, inc. pm6344 equad pmc-951013 issue 5 quadruple e1 framer none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 1998 pmc-sierra, inc. pmc-951013 (r5) ref pmc-950906 (r5) issue date: june 1998 pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 `604 contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com

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